208 lines
5.0 KiB
C
208 lines
5.0 KiB
C
/*
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* Copyright (c) 2017 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK3128_H
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#define _ASM_ARCH_CRU_RK3128_H
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#include <common.h>
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#define MHz 1000000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (594 * MHz)
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#define CPLL_HZ (400 * MHz)
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#define ACLK_BUS_HZ (148500000)
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#define ACLK_PERI_HZ (148500000)
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk3128_clk_priv {
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struct rk3128_cru *cru;
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ulong gpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk3128_cru {
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struct rk3128_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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} pll[4];
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unsigned int cru_mode_con;
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unsigned int cru_clksel_con[35];
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unsigned int cru_clkgate_con[11];
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unsigned int reserved;
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unsigned int cru_glb_srst_fst_value;
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unsigned int cru_glb_srst_snd_value;
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unsigned int reserved1[2];
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unsigned int cru_softrst_con[9];
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unsigned int cru_misc_con;
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unsigned int reserved2[2];
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unsigned int cru_glb_cnt_th;
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unsigned int reserved3[3];
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unsigned int cru_glb_rst_st;
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unsigned int reserved4[(0x1c0 - 0x150) / 4 - 1];
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unsigned int cru_sdmmc_con[2];
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unsigned int cru_sdio_con[2];
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unsigned int reserved5[2];
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unsigned int cru_emmc_con[2];
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unsigned int reserved6[4];
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unsigned int cru_pll_prg_en;
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};
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check_member(rk3128_cru, cru_pll_prg_en, 0x01f0);
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enum rk3128_pll_id {
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APLL,
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DPLL,
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CPLL,
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GPLL,
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PLL_COUNT,
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};
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struct rk3128_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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#define RK2928_PLL_CON(x) ((x) * 0x4)
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#define RK2928_MODE_CON 0x40
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enum {
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/* CRU_CLK_SEL0_CON */
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BUS_PLL_SEL_SHIFT = 13,
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BUS_PLL_SEL_MASK = 3 << BUS_PLL_SEL_SHIFT,
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BUS_PLL_SEL_CPLL = 0,
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BUS_PLL_SEL_GPLL,
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BUS_PLL_SEL_GPLL_DIV2,
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BUS_PLL_SEL_GPLL_DIV3,
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ACLK_BUS_DIV_SHIFT = 8,
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ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 7,
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CORE_CLK_PLL_SEL_MASK = 1 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL_DIV2,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL1_CON */
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PCLK_BUS_DIV_SHIFT = 12,
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PCLK_BUS_DIV_MASK = 7 << PCLK_BUS_DIV_SHIFT,
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HCLK_BUS_DIV_SHIFT = 8,
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HCLK_BUS_DIV_MASK = 3 << HCLK_BUS_DIV_SHIFT,
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CORE_ACLK_DIV_SHIFT = 4,
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CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 0,
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CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT,
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/* CRU_CLK_SEL2_CON */
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NANDC_PLL_SEL_SHIFT = 14,
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NANDC_PLL_SEL_MASK = 3 << NANDC_PLL_SEL_SHIFT,
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NANDC_PLL_SEL_CPLL = 0,
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NANDC_PLL_SEL_GPLL,
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NANDC_CLK_DIV_SHIFT = 8,
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NANDC_CLK_DIV_MASK = 0x1f << NANDC_CLK_DIV_SHIFT,
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PVTM_CLK_DIV_SHIFT = 0,
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PVTM_CLK_DIV_MASK = 0x3f << PVTM_CLK_DIV_SHIFT,
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/* CRU_CLKSEL10_CON */
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PERI_PLL_SEL_SHIFT = 14,
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PERI_PLL_SEL_MASK = 3 << PERI_PLL_SEL_SHIFT,
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PERI_PLL_SEL_GPLL = 0,
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PERI_PLL_SEL_CPLL,
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PERI_PLL_SEL_GPLL_DIV2,
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PERI_PLL_SEL_GPLL_DIV3,
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PCLK_PERI_DIV_SHIFT = 12,
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PCLK_PERI_DIV_MASK = 3 << PCLK_PERI_DIV_SHIFT,
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HCLK_PERI_DIV_SHIFT = 8,
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HCLK_PERI_DIV_MASK = 3 << HCLK_PERI_DIV_SHIFT,
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ACLK_PERI_DIV_SHIFT = 0,
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ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT,
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/* CRU_CLKSEL11_CON */
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SFC_PLL_SEL_SHIFT = 14,
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SFC_PLL_SEL_MASK = 3 << SFC_PLL_SEL_SHIFT,
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SFC_PLL_SEL_CPLL = 0,
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SFC_PLL_SEL_GPLL,
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SFC_CLK_DIV_SHIFT = 8,
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SFC_CLK_DIV_MASK = 0x1f << SFC_CLK_DIV_SHIFT,
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MMC0_PLL_SHIFT = 6,
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MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
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MMC0_SEL_APLL = 0,
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MMC0_SEL_GPLL,
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MMC0_SEL_GPLL_DIV2,
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MMC0_SEL_24M,
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MMC0_DIV_SHIFT = 0,
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MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
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/* CRU_CLKSEL12_CON */
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EMMC_PLL_SHIFT = 14,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_SEL_APLL = 0,
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EMMC_SEL_GPLL,
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EMMC_SEL_GPLL_DIV2,
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EMMC_SEL_24M,
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EMMC_DIV_SHIFT = 8,
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EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
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SDIO_PLL_SHIFT = 6,
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SDIO_PLL_MASK = 3 << SDIO_PLL_SHIFT,
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SDIO_SEL_APLL = 0,
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SDIO_SEL_GPLL,
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SDIO_SEL_GPLL_DIV2,
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SDIO_SEL_24M,
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SDIO_DIV_SHIFT = 0,
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SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT,
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/* CLKSEL_CON24 */
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SARADC_DIV_CON_SHIFT = 8,
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SARADC_DIV_CON_MASK = GENMASK(15, 8),
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SARADC_DIV_CON_WIDTH = 8,
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CLK_CRYPTO_DIV_CON_SHIFT= 0,
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CLK_CRYPTO_DIV_CON_MASK = GENMASK(1, 0),
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/* CLKSEL_CON25 */
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SPI_PLL_SEL_SHIFT = 8,
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SPI_PLL_SEL_MASK = 0x3 << SPI_PLL_SEL_SHIFT,
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SPI_PLL_SEL_CPLL = 0,
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SPI_PLL_SEL_GPLL,
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SPI_PLL_SEL_GPLL_DIV2,
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SPI_DIV_SHIFT = 0,
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SPI_DIV_MASK = 0x7f << SPI_DIV_SHIFT,
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/* CRU_CLKSEL27_CON*/
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DCLK_VOP_SEL_SHIFT = 0,
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DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_PLL_SEL_CPLL = 0,
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DCLK_VOP_DIV_CON_SHIFT = 8,
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DCLK_VOP_DIV_CON_MASK = 0xff << DCLK_VOP_DIV_CON_SHIFT,
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/* CRU_CLKSEL31_CON */
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VIO0_PLL_SHIFT = 5,
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VIO0_PLL_MASK = 7 << VIO0_PLL_SHIFT,
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VI00_SEL_CPLL = 0,
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VIO0_SEL_GPLL,
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VIO0_DIV_SHIFT = 0,
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VIO0_DIV_MASK = 0x1f << VIO0_DIV_SHIFT,
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VIO1_PLL_SHIFT = 13,
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VIO1_PLL_MASK = 7 << VIO1_PLL_SHIFT,
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VI01_SEL_CPLL = 0,
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VIO1_SEL_GPLL,
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VIO1_DIV_SHIFT = 8,
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VIO1_DIV_MASK = 0x1f << VIO1_DIV_SHIFT,
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/* CRU_SOFTRST5_CON */
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DDRCTRL_PSRST_SHIFT = 11,
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DDRCTRL_SRST_SHIFT = 10,
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DDRPHY_PSRST_SHIFT = 9,
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DDRPHY_SRST_SHIFT = 8,
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};
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#endif
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