142 lines
4.9 KiB
Diff
142 lines
4.9 KiB
Diff
From 2dc8450e80b82c481904570dce789843b031db13 Mon Sep 17 00:00:00 2001
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From: Matheus Ferst <matheus.ferst@eldorado.org.br>
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Date: Fri, 17 Dec 2021 17:57:13 +0100
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Subject: [PATCH 18/21] target/ppc: Implement Vector Extract Mask
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Implement the following PowerISA v3.1 instructions:
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vextractbm: Vector Extract Byte Mask
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vextracthm: Vector Extract Halfword Mask
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vextractwm: Vector Extract Word Mask
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vextractdm: Vector Extract Doubleword Mask
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vextractqm: Vector Extract Quadword Mask
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Upstream-Status: Backport
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[https://git.qemu.org/?p=qemu.git;a=commit;h=17868d81e0074905b2c1e414af6618570e8059eb]
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Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Message-Id: <20211203194229.746275-3-matheus.ferst@eldorado.org.br>
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Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
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---
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target/ppc/insn32.decode | 6 +++
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target/ppc/translate/vmx-impl.c.inc | 82 +++++++++++++++++++++++++++++
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2 files changed, 88 insertions(+)
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diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
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index e032251c74..b0568b1356 100644
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--- a/target/ppc/insn32.decode
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+++ b/target/ppc/insn32.decode
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@@ -423,6 +423,12 @@ VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb
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VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb
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VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb
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+VEXTRACTBM 000100 ..... 01000 ..... 11001000010 @VX_tb
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+VEXTRACTHM 000100 ..... 01001 ..... 11001000010 @VX_tb
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+VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb
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+VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb
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+VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb
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+
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# VSX Load/Store Instructions
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LXV 111101 ..... ..... ............ . 001 @DQ_TSX
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diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
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index ebb0484323..96c97bf6e7 100644
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--- a/target/ppc/translate/vmx-impl.c.inc
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+++ b/target/ppc/translate/vmx-impl.c.inc
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@@ -1525,6 +1525,88 @@ static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
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return true;
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}
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+static bool do_vextractm(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
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+{
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+ const uint64_t elem_width = 8 << vece, elem_count_half = 8 >> vece,
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+ mask = dup_const(vece, 1 << (elem_width - 1));
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+ uint64_t i, j;
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+ TCGv_i64 lo, hi, t0, t1;
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+
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+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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+ REQUIRE_VECTOR(ctx);
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+
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+ hi = tcg_temp_new_i64();
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+ lo = tcg_temp_new_i64();
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+ t0 = tcg_temp_new_i64();
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+ t1 = tcg_temp_new_i64();
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+
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+ get_avr64(lo, a->vrb, false);
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+ get_avr64(hi, a->vrb, true);
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+
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+ tcg_gen_andi_i64(lo, lo, mask);
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+ tcg_gen_andi_i64(hi, hi, mask);
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+
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+ /*
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+ * Gather the most significant bit of each element in the highest element
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+ * element. E.g. for bytes:
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+ * aXXXXXXXbXXXXXXXcXXXXXXXdXXXXXXXeXXXXXXXfXXXXXXXgXXXXXXXhXXXXXXX
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+ * & dup(1 << (elem_width - 1))
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+ * a0000000b0000000c0000000d0000000e0000000f0000000g0000000h0000000
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+ * << 32 - 4
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+ * 0000e0000000f0000000g0000000h00000000000000000000000000000000000
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+ * |
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+ * a000e000b000f000c000g000d000h000e0000000f0000000g0000000h0000000
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+ * << 16 - 2
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+ * 00c000g000d000h000e0000000f0000000g0000000h000000000000000000000
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+ * |
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+ * a0c0e0g0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h0000000
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+ * << 8 - 1
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+ * 0b0d0f0h0c0e0g000d0f0h000e0g00000f0h00000g0000000h00000000000000
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+ * |
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+ * abcdefghbcdefgh0cdefgh00defgh000efgh0000fgh00000gh000000h0000000
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+ */
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+ for (i = elem_count_half / 2, j = 32; i > 0; i >>= 1, j >>= 1) {
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+ tcg_gen_shli_i64(t0, hi, j - i);
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+ tcg_gen_shli_i64(t1, lo, j - i);
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+ tcg_gen_or_i64(hi, hi, t0);
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+ tcg_gen_or_i64(lo, lo, t1);
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+ }
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+
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+ tcg_gen_shri_i64(hi, hi, 64 - elem_count_half);
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+ tcg_gen_extract2_i64(lo, lo, hi, 64 - elem_count_half);
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+ tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], lo);
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+
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+ tcg_temp_free_i64(hi);
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+ tcg_temp_free_i64(lo);
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+ tcg_temp_free_i64(t0);
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+ tcg_temp_free_i64(t1);
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+
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+ return true;
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+}
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+
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+TRANS(VEXTRACTBM, do_vextractm, MO_8)
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+TRANS(VEXTRACTHM, do_vextractm, MO_16)
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+TRANS(VEXTRACTWM, do_vextractm, MO_32)
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+TRANS(VEXTRACTDM, do_vextractm, MO_64)
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+
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+static bool trans_VEXTRACTQM(DisasContext *ctx, arg_VX_tb *a)
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+{
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+ TCGv_i64 tmp;
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+
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+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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+ REQUIRE_VECTOR(ctx);
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+
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+ tmp = tcg_temp_new_i64();
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+
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+ get_avr64(tmp, a->vrb, true);
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+ tcg_gen_shri_i64(tmp, tmp, 63);
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+ tcg_gen_trunc_i64_tl(cpu_gpr[a->vrt], tmp);
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+
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+ tcg_temp_free_i64(tmp);
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+
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+ return true;
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+}
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+
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#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
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static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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{ \
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--
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2.17.1
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