106 lines
3.5 KiB
Diff
106 lines
3.5 KiB
Diff
From 4c6a16c2bcdd14249eef876d3d029c445716fb13 Mon Sep 17 00:00:00 2001
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From: Matheus Ferst <matheus.ferst@eldorado.org.br>
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Date: Fri, 17 Dec 2021 17:57:13 +0100
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Subject: [PATCH 17/21] target/ppc: Implement Vector Expand Mask
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Implement the following PowerISA v3.1 instructions:
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vexpandbm: Vector Expand Byte Mask
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vexpandhm: Vector Expand Halfword Mask
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vexpandwm: Vector Expand Word Mask
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vexpanddm: Vector Expand Doubleword Mask
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vexpandqm: Vector Expand Quadword Mask
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Upstream-Status: Backport
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[https://git.qemu.org/?p=qemu.git;a=commit;h=5f1470b091007f24035d6d33149df49a6dd61682]
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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
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Message-Id: <20211203194229.746275-2-matheus.ferst@eldorado.org.br>
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Signed-off-by: Cédric Le Goater <clg@kaod.org>
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Signed-off-by: Xiangyu Chen <xiangyu.chen@windriver.com>
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---
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target/ppc/insn32.decode | 11 ++++++++++
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target/ppc/translate/vmx-impl.c.inc | 34 +++++++++++++++++++++++++++++
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2 files changed, 45 insertions(+)
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diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
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index fd6bb13fa0..e032251c74 100644
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--- a/target/ppc/insn32.decode
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+++ b/target/ppc/insn32.decode
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@@ -56,6 +56,9 @@
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&VX_uim4 vrt uim vrb
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@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
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+&VX_tb vrt vrb
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+@VX_tb ...... vrt:5 ..... vrb:5 ........... &VX_tb
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+
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&X rt ra rb
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@X ...... rt:5 ra:5 rb:5 .......... . &X
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@@ -412,6 +415,14 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
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VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
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VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
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+## Vector Mask Manipulation Instructions
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+
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+VEXPANDBM 000100 ..... 00000 ..... 11001000010 @VX_tb
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+VEXPANDHM 000100 ..... 00001 ..... 11001000010 @VX_tb
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+VEXPANDWM 000100 ..... 00010 ..... 11001000010 @VX_tb
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+VEXPANDDM 000100 ..... 00011 ..... 11001000010 @VX_tb
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+VEXPANDQM 000100 ..... 00100 ..... 11001000010 @VX_tb
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+
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# VSX Load/Store Instructions
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LXV 111101 ..... ..... ............ . 001 @DQ_TSX
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diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
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index 8eb8d3a067..ebb0484323 100644
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--- a/target/ppc/translate/vmx-impl.c.inc
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+++ b/target/ppc/translate/vmx-impl.c.inc
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@@ -1491,6 +1491,40 @@ static bool trans_VSRDBI(DisasContext *ctx, arg_VN *a)
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return true;
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}
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+static bool do_vexpand(DisasContext *ctx, arg_VX_tb *a, unsigned vece)
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+{
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+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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+ REQUIRE_VECTOR(ctx);
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+
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+ tcg_gen_gvec_sari(vece, avr_full_offset(a->vrt), avr_full_offset(a->vrb),
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+ (8 << vece) - 1, 16, 16);
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+
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+ return true;
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+}
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+
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+TRANS(VEXPANDBM, do_vexpand, MO_8)
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+TRANS(VEXPANDHM, do_vexpand, MO_16)
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+TRANS(VEXPANDWM, do_vexpand, MO_32)
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+TRANS(VEXPANDDM, do_vexpand, MO_64)
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+
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+static bool trans_VEXPANDQM(DisasContext *ctx, arg_VX_tb *a)
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+{
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+ TCGv_i64 tmp;
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+
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+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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+ REQUIRE_VECTOR(ctx);
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+
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+ tmp = tcg_temp_new_i64();
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+
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+ get_avr64(tmp, a->vrb, true);
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+ tcg_gen_sari_i64(tmp, tmp, 63);
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+ set_avr64(a->vrt, tmp, false);
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+ set_avr64(a->vrt, tmp, true);
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+
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+ tcg_temp_free_i64(tmp);
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+ return true;
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+}
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+
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#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
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static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
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{ \
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--
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2.17.1
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