2493 lines
64 KiB
Plaintext
2493 lines
64 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
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*/
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#include <dt-bindings/clock/rk3368-cru.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/power/rk3368-power.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/soc/rockchip-system-status.h>
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#include <dt-bindings/suspend/rockchip-rk3368.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/display/mipi_dsi.h>
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#include <dt-bindings/display/drm_mipi_dsi.h>
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#include <dt-bindings/display/media-bus-format.h>
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#include "rk3368-dram-default-timing.dtsi"
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/ {
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compatible = "rockchip,rk3368";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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ethernet0 = &gmac;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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mmc0 = &sdmmc;
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mmc1 = &sdio0;
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mmc2 = &emmc;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_l0>;
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};
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core1 {
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cpu = <&cpu_l1>;
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};
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core2 {
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cpu = <&cpu_l2>;
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};
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core3 {
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cpu = <&cpu_l3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_b0>;
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};
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core1 {
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cpu = <&cpu_b1>;
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};
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core2 {
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cpu = <&cpu_b2>;
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};
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core3 {
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cpu = <&cpu_b3>;
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};
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};
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};
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cpu_l0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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next-level-cache = <&cluster0_l2>;
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operating-points-v2 = <&cluster0_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <149>;
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};
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cpu_l1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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next-level-cache = <&cluster0_l2>;
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operating-points-v2 = <&cluster0_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
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};
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cpu_l2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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next-level-cache = <&cluster0_l2>;
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operating-points-v2 = <&cluster0_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
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};
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cpu_l3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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clocks = <&cru ARMCLKL>;
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next-level-cache = <&cluster0_l2>;
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operating-points-v2 = <&cluster0_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
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};
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cpu_b0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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next-level-cache = <&cluster1_l2>;
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operating-points-v2 = <&cluster1_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
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#cooling-cells = <2>; /* min followed by max */
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dynamic-power-coefficient = <160>;
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};
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cpu_b1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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next-level-cache = <&cluster1_l2>;
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operating-points-v2 = <&cluster1_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
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};
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cpu_b2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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next-level-cache = <&cluster1_l2>;
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operating-points-v2 = <&cluster1_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
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};
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cpu_b3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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clocks = <&cru ARMCLKB>;
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next-level-cache = <&cluster1_l2>;
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operating-points-v2 = <&cluster1_opp>;
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sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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rockchip,leakage-voltage-sel = <
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1 24 0
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25 254 1
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>;
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nvmem-cells = <&cpu_leakage>, <&leakage_temp>, <&leakage_volt>;
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nvmem-cell-names = "cpu_leakage", "leakage_temp",
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"leakage_volt";
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rockchip,reboot-freq = <816000>;
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opp-216000000 {
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opp-hz = /bits/ 64 <216000000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <1050000 1050000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <1050000 1050000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <1050000 1050000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <1025000 1025000 1350000>;
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opp-microvolt-L0 = <1125000 1125000 1350000>;
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opp-microvolt-L1 = <1025000 1025000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1125000 1125000 1350000>;
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opp-microvolt-L0 = <1225000 1225000 1350000>;
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opp-microvolt-L1 = <1125000 1125000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1225000 1225000 1350000>;
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opp-microvolt-L0 = <1325000 1325000 1350000>;
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opp-microvolt-L1 = <1225000 1225000 1350000>;
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clock-latency-ns = <40000>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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rockchip,avs-sclae = <36>;
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rockchip,leakage-scaling-sel = <
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1 24 36
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25 254 0
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>;
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clocks = <&cru PLL_APLLB>;
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rockchip,leakage-voltage-sel = <
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1 24 0
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25 50 1
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51 254 2
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>;
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nvmem-cells = <&cpu_leakage>, <&leakage_temp>, <&leakage_volt>;
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nvmem-cell-names = "cpu_leakage", "leakage_temp",
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"leakage_volt";
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rockchip,reboot-freq = <816000>;
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opp-216000000 {
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opp-hz = /bits/ 64 <216000000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <1050000 1050000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-408000000 {
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <1050000 1050000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <950000 950000 1350000>;
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opp-microvolt-L0 = <1050000 1050000 1350000>;
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opp-microvolt-L1 = <950000 950000 1350000>;
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opp-microvolt-L2 = <950000 950000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-816000000 {
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <975000 975000 1350000>;
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opp-microvolt-L0 = <1075000 1075000 1350000>;
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opp-microvolt-L1 = <975000 975000 1350000>;
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opp-microvolt-L2 = <975000 975000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1008000000 {
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opp-hz = /bits/ 64 <1008000000>;
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opp-microvolt = <1050000 1050000 1350000>;
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opp-microvolt-L0 = <1150000 1150000 1350000>;
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opp-microvolt-L1 = <1050000 1050000 1350000>;
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opp-microvolt-L2 = <1025000 1025000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1200000000 {
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opp-hz = /bits/ 64 <1200000000>;
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opp-microvolt = <1150000 1150000 1350000>;
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opp-microvolt-L0 = <1250000 1250000 1350000>;
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opp-microvolt-L1 = <1150000 1150000 1350000>;
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opp-microvolt-L2 = <1125000 1125000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1296000000 {
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opp-hz = /bits/ 64 <1296000000>;
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opp-microvolt = <1225000 1225000 1350000>;
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opp-microvolt-L0 = <1350000 1350000 1350000>;
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opp-microvolt-L1 = <1225000 1225000 1350000>;
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opp-microvolt-L2 = <1200000 1200000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <1300000 1300000 1350000>;
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opp-microvolt-L0 = <1350000 1350000 1350000>;
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opp-microvolt-L1 = <1300000 1300000 1350000>;
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opp-microvolt-L2 = <1275000 1275000 1350000>;
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clock-latency-ns = <40000>;
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};
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opp-1512000000 {
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opp-hz = /bits/ 64 <1512000000>;
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opp-microvolt = <1350000 1350000 1350000>;
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opp-microvolt-L0 = <1350000 1350000 1350000>;
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opp-microvolt-L1 = <1350000 1350000 1350000>;
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opp-microvolt-L2 = <1325000 1325000 1350000>;
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clock-latency-ns = <40000>;
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};
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};
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energy-costs {
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RK3368_CPU_COST_0: rk3368-core-cost0 {
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busy-cost-data = <
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146 44 /* 216M */
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276 72 /* 408M */
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406 99 /* 600M */
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552 147 /* 816M */
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682 200 /* 1008M */
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812 255 /* 1200M */
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>;
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idle-cost-data = <
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6
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6
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0
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>;
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};
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RK3368_CPU_COST_1: rk3368-core-cost1 {
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busy-cost-data = <
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146 53 /* 216M */
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276 86 /* 408M */
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406 118 /* 600M */
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552 166 /* 816M */
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682 226 /* 1008M */
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812 309 /* 1200M */
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878 371 /* 1200M */
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959 446 /* 1416M */
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1024 513 /* 1512M */
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>;
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idle-cost-data = <
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6
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6
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0
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>;
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};
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RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
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busy-cost-data = <
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146 9 /* 216M */
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276 14 /* 408M */
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406 20 /* 600M */
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552 29 /* 816M */
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682 40 /* 1008M */
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812 51 /* 1200M */
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>;
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idle-cost-data = <
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56
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56
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56
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>;
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};
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RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
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busy-cost-data = <
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146 11 /* 216M */
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276 17 /* 408M */
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406 24 /* 600M */
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552 33 /* 816M */
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682 45 /* 1008M */
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812 62 /* 1200M */
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878 74 /* 1200M */
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959 89 /* 1416M */
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1024 103 /* 1512M */
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>;
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idle-cost-data = <
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56
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56
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56
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>;
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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dmac_peri: dma-controller@ff250000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff250000 0x0 0x4000>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMAC_PERI>;
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clock-names = "apb_pclk";
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};
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dmac_bus: dma-controller@ff600000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x0 0xff600000 0x0 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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arm,pl330-broken-no-flushp;
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arm,pl330-periph-burst;
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clocks = <&cru ACLK_DMAC_BUS>;
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clock-names = "apb_pclk";
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};
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};
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arm-pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
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<&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
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<&cpu_b2>, <&cpu_b3>;
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};
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firmware {
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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|
xin24m: oscillator {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <24000000>;
|
|
clock-output-names = "xin24m";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
sdmmc: dwmmc@ff0c0000 {
|
|
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xff0c0000 0x0 0x4000>;
|
|
max-frequency = <150000000>;
|
|
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
|
|
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&cru SRST_MMC0>;
|
|
reset-names = "reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
sdio0: dwmmc@ff0d0000 {
|
|
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xff0d0000 0x0 0x4000>;
|
|
max-frequency = <150000000>;
|
|
clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
|
|
<&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&cru SRST_SDIO0>;
|
|
reset-names = "reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
emmc: dwmmc@ff0f0000 {
|
|
compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
|
|
reg = <0x0 0xff0f0000 0x0 0x4000>;
|
|
max-frequency = <150000000>;
|
|
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
|
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
|
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
|
|
fifo-depth = <0x100>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
resets = <&cru SRST_EMMC>;
|
|
reset-names = "reset";
|
|
status = "disabled";
|
|
};
|
|
|
|
saradc: saradc@ff100000 {
|
|
compatible = "rockchip,saradc";
|
|
reg = <0x0 0xff100000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
#io-channel-cells = <1>;
|
|
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
|
|
clock-names = "saradc", "apb_pclk";
|
|
resets = <&cru SRST_SARADC>;
|
|
reset-names = "saradc-apb";
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@ff110000 {
|
|
compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff110000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@ff120000 {
|
|
compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff120000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi2: spi@ff130000 {
|
|
compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
|
|
reg = <0x0 0xff130000 0x0 0x1000>;
|
|
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
|
|
clock-names = "spiclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@ff650000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff650000 0x0 0x1000>;
|
|
clocks = <&cru PCLK_I2C0>;
|
|
clock-names = "i2c";
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c0_xfer>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@ff140000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff140000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c2_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@ff150000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff150000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C3>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@ff160000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff160000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C4>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c@ff170000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff170000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C5>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@ff180000 {
|
|
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff180000 0x0 0x100>;
|
|
clock-frequency = <24000000>;
|
|
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@ff190000 {
|
|
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff190000 0x0 0x100>;
|
|
clock-frequency = <24000000>;
|
|
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@ff1b0000 {
|
|
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff1b0000 0x0 0x100>;
|
|
clock-frequency = <24000000>;
|
|
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@ff1c0000 {
|
|
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff1c0000 0x0 0x100>;
|
|
clock-frequency = <24000000>;
|
|
clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
soc_thermal: soc-thermal {
|
|
polling-delay-passive = <200>; /* milliseconds */
|
|
polling-delay = <200>; /* milliseconds */
|
|
sustainable-power = <600>; /* milliwatts */
|
|
|
|
thermal-sensors = <&tsadc 0>;
|
|
trips {
|
|
threshold: trip-point-0 {
|
|
temperature = <70000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
target: trip-point-1 {
|
|
temperature = <80000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "passive";
|
|
};
|
|
soc_crit: soc-crit {
|
|
temperature = <115000>; /* millicelsius */
|
|
hysteresis = <2000>; /* millicelsius */
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&target>;
|
|
cooling-device =
|
|
<&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
contribution = <1024>;
|
|
};
|
|
map1 {
|
|
trip = <&target>;
|
|
cooling-device =
|
|
<&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
contribution = <1024>;
|
|
};
|
|
map2 {
|
|
trip = <&target>;
|
|
cooling-device =
|
|
<&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
contribution = <1024>;
|
|
};
|
|
};
|
|
};
|
|
|
|
gpu_thermal: gpu-thermal {
|
|
polling-delay-passive = <200>; /* milliseconds */
|
|
polling-delay = <200>; /* milliseconds */
|
|
thermal-sensors = <&tsadc 1>;
|
|
};
|
|
};
|
|
|
|
tsadc: tsadc@ff280000 {
|
|
compatible = "rockchip,rk3368-tsadc-legacy";
|
|
reg = <0x0 0xff280000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
|
|
clock-names = "tsadc", "apb_pclk";
|
|
clock-frequency = <32768>;
|
|
resets = <&cru SRST_TSADC>;
|
|
reset-names = "tsadc-apb";
|
|
nvmem-cells = <&temp_adjust>;
|
|
nvmem-cell-names = "temp_adjust";
|
|
#thermal-sensor-cells = <1>;
|
|
hw-shut-temp = <95000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac: ethernet@ff290000 {
|
|
compatible = "rockchip,rk3368-gmac";
|
|
reg = <0x0 0xff290000 0x0 0x10000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "macirq";
|
|
rockchip,grf = <&grf>;
|
|
clocks = <&cru SCLK_MAC>,
|
|
<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
|
|
<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
|
|
<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
|
|
clock-names = "stmmaceth",
|
|
"mac_clk_rx", "mac_clk_tx",
|
|
"clk_mac_ref", "clk_mac_refout",
|
|
"aclk_mac", "pclk_mac";
|
|
status = "disabled";
|
|
};
|
|
|
|
nandc0: nandc@ff400000 {
|
|
compatible = "rockchip,rk-nandc";
|
|
reg = <0x0 0xff400000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
nandc_id = <0>;
|
|
clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
|
|
clock-names = "clk_nandc", "hclk_nandc";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host0_ehci: usb@ff500000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x0 0xff500000 0x0 0x20000>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST0>, <&u2phy>;
|
|
clock-names = "usbhost", "utmi";
|
|
phys = <&u2phy_host>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_host0_ohci: usb@ff520000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0x0 0xff520000 0x0 0x20000>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_HOST0>, <&u2phy>;
|
|
clock-names = "usbhost", "utmi";
|
|
phys = <&u2phy_host>;
|
|
phy-names = "usb";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_otg: usb@ff580000 {
|
|
compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
|
|
"snps,dwc2";
|
|
reg = <0x0 0xff580000 0x0 0x40000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru HCLK_OTG0>;
|
|
clock-names = "otg";
|
|
dr_mode = "otg";
|
|
g-np-tx-fifo-size = <16>;
|
|
g-rx-fifo-size = <280>;
|
|
g-tx-fifo-size = <256 128 128 64 32 16>;
|
|
g-use-dma;
|
|
phys = <&u2phy_otg>;
|
|
phy-names = "usb2-phy";
|
|
status = "disabled";
|
|
};
|
|
|
|
ddrpctl: syscon@ff610000 {
|
|
compatible = "rockchip,rk3368-ddrpctl", "syscon";
|
|
reg = <0x0 0xff610000 0x0 0x400>;
|
|
};
|
|
|
|
i2c1: i2c@ff660000 {
|
|
compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
|
|
reg = <0x0 0xff660000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-names = "i2c";
|
|
clocks = <&cru PCLK_I2C1>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c1_xfer>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@ff680000 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680000 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm0_pin>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@ff680010 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680010 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm1_pin>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@ff680020 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680020 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@ff680030 {
|
|
compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
|
|
reg = <0x0 0xff680030 0x0 0x10>;
|
|
#pwm-cells = <3>;
|
|
pinctrl-names = "active";
|
|
pinctrl-0 = <&pwm3_pin>;
|
|
clocks = <&cru PCLK_PWM1>;
|
|
clock-names = "pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@ff690000 {
|
|
compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
|
|
reg = <0x0 0xff690000 0x0 0x100>;
|
|
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
|
clock-names = "baudclk", "apb_pclk";
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart2_xfer>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mbox: mbox@ff6b0000 {
|
|
compatible = "rockchip,rk3368-mailbox";
|
|
reg = <0x0 0xff6b0000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_MAILBOX>;
|
|
clock-names = "pclk_mailbox";
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mailbox: mailbox@ff6b0000 {
|
|
compatible = "rockchip,rk3368-mbox-legacy";
|
|
reg = <0x0 0xff6b0000 0x0 0x1000>,
|
|
<0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_MAILBOX>;
|
|
clock-names = "pclk_mailbox";
|
|
#mbox-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mailbox_scpi: mailbox-scpi {
|
|
compatible = "rockchip,rk3368-scpi-legacy";
|
|
mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
|
|
chan-nums = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
qos_iep: qos@ffad0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0000 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp_r0: qos@ffad0080 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0080 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp_r1: qos@ffad0100 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0100 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp_w0: qos@ffad0180 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0180 0x0 0x20>;
|
|
};
|
|
|
|
qos_isp_w1: qos@ffad0200 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0200 0x0 0x20>;
|
|
};
|
|
|
|
qos_vip: qos@ffad0280 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0280 0x0 0x20>;
|
|
};
|
|
|
|
qos_vop: qos@ffad0300 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0300 0x0 0x20>;
|
|
};
|
|
|
|
qos_rga_r: qos@ffad0380 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0380 0x0 0x20>;
|
|
};
|
|
|
|
qos_rga_w: qos@ffad0400 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffad0400 0x0 0x20>;
|
|
};
|
|
|
|
qos_hevc_r: qos@ffae0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffae0000 0x0 0x20>;
|
|
};
|
|
|
|
qos_vpu_r: qos@ffae0100 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffae0100 0x0 0x20>;
|
|
};
|
|
|
|
qos_vpu_w: qos@ffae0180 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffae0180 0x0 0x20>;
|
|
};
|
|
|
|
qos_gpu: qos@ffaf0000 {
|
|
compatible = "syscon";
|
|
reg = <0x0 0xffaf0000 0x0 0x20>;
|
|
};
|
|
|
|
pmu: power-management@ff730000 {
|
|
compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff730000 0x0 0x1000>;
|
|
|
|
power: power-controller {
|
|
compatible = "rockchip,rk3368-power-controller";
|
|
#power-domain-cells = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
/*
|
|
* Note: Although SCLK_* are the working clocks
|
|
* of device without including on the NOC, needed for
|
|
* synchronous reset.
|
|
*
|
|
* The clocks on the which NOC:
|
|
* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
|
|
* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
|
|
* ACLK_RGA is on ACLK_RGA_NIU.
|
|
* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
|
|
*
|
|
* Which clock are device clocks:
|
|
* clocks devices
|
|
* *_IEP IEP:Image Enhancement Processor
|
|
* *_ISP ISP:Image Signal Processing
|
|
* *_VIP VIP:Video Input Processor
|
|
* *_VOP* VOP:Visual Output Processor
|
|
* *_RGA RGA
|
|
* *_EDP* EDP
|
|
* *_DPHY* LVDS
|
|
* *_HDMI HDMI
|
|
* *_MIPI_* MIPI
|
|
*/
|
|
pd_vio@RK3368_PD_VIO {
|
|
reg = <RK3368_PD_VIO>;
|
|
clocks = <&cru ACLK_IEP>,
|
|
<&cru ACLK_ISP>,
|
|
<&cru ACLK_VIP>,
|
|
<&cru ACLK_RGA>,
|
|
<&cru ACLK_VOP>,
|
|
<&cru ACLK_VOP_IEP>,
|
|
<&cru DCLK_VOP>,
|
|
<&cru HCLK_IEP>,
|
|
<&cru HCLK_ISP>,
|
|
<&cru HCLK_RGA>,
|
|
<&cru HCLK_VIP>,
|
|
<&cru HCLK_VOP>,
|
|
<&cru HCLK_VIO_HDCPMMU>,
|
|
<&cru PCLK_EDP_CTRL>,
|
|
<&cru PCLK_HDMI_CTRL>,
|
|
<&cru PCLK_HDCP>,
|
|
<&cru PCLK_ISP>,
|
|
<&cru PCLK_VIP>,
|
|
<&cru PCLK_DPHYRX>,
|
|
<&cru PCLK_DPHYTX0>,
|
|
<&cru PCLK_MIPI_CSI>,
|
|
<&cru PCLK_MIPI_DSI0>,
|
|
<&cru SCLK_VOP0_PWM>,
|
|
<&cru SCLK_EDP_24M>,
|
|
<&cru SCLK_EDP>,
|
|
<&cru SCLK_HDCP>,
|
|
<&cru SCLK_ISP>,
|
|
<&cru SCLK_RGA>,
|
|
<&cru SCLK_HDMI_CEC>,
|
|
<&cru SCLK_HDMI_HDCP>;
|
|
pm_qos = <&qos_iep>,
|
|
<&qos_isp_r0>,
|
|
<&qos_isp_r1>,
|
|
<&qos_isp_w0>,
|
|
<&qos_isp_w1>,
|
|
<&qos_vip>,
|
|
<&qos_vop>,
|
|
<&qos_rga_r>,
|
|
<&qos_rga_w>;
|
|
};
|
|
/*
|
|
* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
|
|
* (video endecoder & decoder) clocks that on the
|
|
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
|
|
*/
|
|
pd_video@RK3368_PD_VIDEO {
|
|
reg = <RK3368_PD_VIDEO>;
|
|
clocks = <&cru ACLK_VIDEO>,
|
|
<&cru HCLK_VIDEO>,
|
|
<&cru SCLK_HEVC_CABAC>,
|
|
<&cru SCLK_HEVC_CORE>;
|
|
pm_qos = <&qos_hevc_r>,
|
|
<&qos_vpu_r>,
|
|
<&qos_vpu_w>;
|
|
};
|
|
/*
|
|
* Note: ACLK_GPU is the GPU clock,
|
|
* and on the ACLK_GPU_NIU (NOC).
|
|
*/
|
|
pd_gpu_1@RK3368_PD_GPU_1 {
|
|
reg = <RK3368_PD_GPU_1>;
|
|
clocks = <&cru ACLK_GPU_CFG>,
|
|
<&cru ACLK_GPU_MEM>,
|
|
<&cru SCLK_GPU_CORE>;
|
|
pm_qos = <&qos_gpu>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pmugrf: syscon@ff738000 {
|
|
compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff738000 0x0 0x1000>;
|
|
|
|
pmu_io_domains: io-domains {
|
|
compatible = "rockchip,rk3368-pmu-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
|
|
pvtm_clock: pvtm-clock {
|
|
compatible = "rockchip,rk3368-pvtm-clock";
|
|
#clock-cells = <0>;
|
|
clocks = <&cru SCLK_PVTM_PMU>;
|
|
clock-names = "pvtm_pmu_clk";
|
|
clock-output-names = "xin32k_pvtm";
|
|
status = "okay";
|
|
};
|
|
|
|
reboot_mode: reboot-mode {
|
|
compatible = "syscon-reboot-mode";
|
|
offset = <0x200>;
|
|
mode-normal = <BOOT_NORMAL>;
|
|
mode-recovery = <BOOT_RECOVERY>;
|
|
mode-bootloader = <BOOT_FASTBOOT>;
|
|
mode-loader = <BOOT_BL_DOWNLOAD>;
|
|
};
|
|
};
|
|
|
|
cru: clock-controller@ff760000 {
|
|
compatible = "rockchip,rk3368-cru";
|
|
reg = <0x0 0xff760000 0x0 0x1000>;
|
|
rockchip,grf = <&grf>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
assigned-clocks =
|
|
<&cru ARMCLKL>, <&cru ARMCLKB>,
|
|
<&cru PLL_GPLL>, <&cru PLL_CPLL>,
|
|
<&cru ACLK_BUS>, <&cru ACLK_PERI>,
|
|
<&cru HCLK_BUS>, <&cru HCLK_PERI>,
|
|
<&cru PCLK_BUS>, <&cru PCLK_PERI>,
|
|
<&cru ACLK_CCI_PRE>;
|
|
assigned-clock-rates =
|
|
<600000000>, <600000000>,
|
|
<576000000>, <400000000>,
|
|
<300000000>, <300000000>,
|
|
<150000000>, <150000000>,
|
|
<75000000>, <75000000>,
|
|
<576000000>;
|
|
};
|
|
|
|
grf: syscon@ff770000 {
|
|
compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
|
|
reg = <0x0 0xff770000 0x0 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
io_domains: io-domains {
|
|
compatible = "rockchip,rk3368-io-voltage-domain";
|
|
status = "disabled";
|
|
};
|
|
|
|
lvds: lvds {
|
|
compatible = "rockchip,rk3368-lvds";
|
|
phys = <&video_phy>;
|
|
phy-names = "phy";
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
lvds_in_vop: endpoint {
|
|
remote-endpoint = <&vop_out_lvds>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
rgb: rgb {
|
|
compatible = "rockchip,rk3368-rgb";
|
|
phys = <&video_phy>;
|
|
phy-names = "phy";
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <&lcdc_rgb_pins>;
|
|
pinctrl-1 = <&lcdc_sleep_pins>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
rgb_in_vop: endpoint {
|
|
remote-endpoint = <&vop_out_rgb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
u2phy: usb2-phy@700 {
|
|
compatible = "rockchip,rk3368-usb2phy";
|
|
reg = <0x700 0x2c>;
|
|
clocks = <&cru SCLK_OTGPHY0>;
|
|
clock-names = "phyclk";
|
|
#clock-cells = <0>;
|
|
clock-output-names = "usbotg_out";
|
|
assigned-clocks = <&cru SCLK_USBPHY480M>;
|
|
assigned-clock-parents = <&u2phy>;
|
|
status = "disabled";
|
|
|
|
u2phy_otg: otg-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "otg-bvalid", "otg-id",
|
|
"linestate";
|
|
status = "disabled";
|
|
};
|
|
|
|
u2phy_host: host-port {
|
|
#phy-cells = <0>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "linestate";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dfi: dfi {
|
|
compatible = "rockchip,rk3368-dfi";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dmc: dmc {
|
|
compatible = "rockchip,rk3368-dmc";
|
|
devfreq-events = <&dfi>;
|
|
clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_DDRPHY>,
|
|
<&cru PCLK_DDRUPCTL>;
|
|
clock-names = "dmc_clk", "pclk_phy", "pclk_upctl";
|
|
ddr_timing = <&ddr_timing>;
|
|
upthreshold = <50>;
|
|
downdifferential = <20>;
|
|
operating-points-v2 = <&dmc_opp_table>;
|
|
vop-dclk-mode = <0>;
|
|
system-status-freq = <
|
|
/*system status freq(KHz)*/
|
|
SYS_STATUS_NORMAL 600000
|
|
SYS_STATUS_REBOOT 600000
|
|
SYS_STATUS_SUSPEND 192000
|
|
SYS_STATUS_VIDEO_1080P 300000
|
|
SYS_STATUS_VIDEO_4K 600000
|
|
SYS_STATUS_PERFORMANCE 600000
|
|
SYS_STATUS_BOOST 396000
|
|
SYS_STATUS_DUALVIEW 600000
|
|
SYS_STATUS_ISP 528000
|
|
>;
|
|
auto-min-freq = <396000>;
|
|
auto-freq-en = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dmc_opp_table: opp_table2 {
|
|
compatible = "operating-points-v2";
|
|
|
|
opp-192000000 {
|
|
opp-hz = /bits/ 64 <192000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
|
|
opp-240000000 {
|
|
opp-hz = /bits/ 64 <240000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
|
|
opp-300000000 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
opp-396000000 {
|
|
opp-hz = /bits/ 64 <396000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
opp-528000000 {
|
|
opp-hz = /bits/ 64 <528000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
opp-600000000 {
|
|
opp-hz = /bits/ 64 <600000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
};
|
|
|
|
wdt: watchdog@ff800000 {
|
|
compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
|
|
reg = <0x0 0xff800000 0x0 0x100>;
|
|
clocks = <&cru PCLK_WDT>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@ff810000 {
|
|
compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
|
|
reg = <0x0 0xff810000 0x0 0x20>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
spdif: spdif@ff880000 {
|
|
compatible = "rockchip,rk3368-spdif";
|
|
reg = <0x0 0xff880000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
|
|
clock-names = "mclk", "hclk";
|
|
dmas = <&dmac_bus 3>;
|
|
dma-names = "tx";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spdif_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_2ch: i2s-2ch@ff890000 {
|
|
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff890000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
|
|
dmas = <&dmac_bus 6>, <&dmac_bus 7>;
|
|
dma-names = "tx", "rx";
|
|
resets = <&cru SRST_I2S2CH>;
|
|
reset-names = "reset-m";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s_8ch: i2s-8ch@ff898000 {
|
|
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
|
|
reg = <0x0 0xff898000 0x0 0x1000>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-names = "i2s_clk", "i2s_hclk";
|
|
clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
|
|
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
|
|
dma-names = "tx", "rx";
|
|
resets = <&cru SRST_I2S8CH>;
|
|
reset-names = "reset-m";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s_8ch_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rng: rng@ff8a0000 {
|
|
compatible = "rockchip,cryptov1-rng";
|
|
reg = <0x0 0xff8a0000 0x0 0x4000>;
|
|
|
|
clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
|
|
clock-names = "clk_crypto", "hclk_crypto";
|
|
assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO>;
|
|
assigned-clock-rates = <150000000>, <100000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep: iep@ff900000 {
|
|
compatible = "rockchip,iep";
|
|
iommu_enabled = <1>;
|
|
iommus = <&iep_mmu>;
|
|
reg = <0x0 0xff900000 0x0 0x800>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
|
|
clock-names = "aclk_iep", "hclk_iep";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
allocator = <1>;
|
|
version = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
iep_mmu: iommu@ff900800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff900800 0x0 0x100>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "iep_mmu";
|
|
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
isp: isp@ff910000 {
|
|
compatible = "rockchip,rk3368-isp", "rockchip,isp";
|
|
reg = <0x0 0xff910000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
clocks =
|
|
<&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
|
|
<&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
|
|
<&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
|
|
<&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
|
|
clock-names =
|
|
"aclk_isp", "hclk_isp", "clk_isp",
|
|
"clk_isp_jpe", "pclkin_isp", "clk_cif_out",
|
|
"clk_cif_pll", "hclk_mipiphy1",
|
|
"pclk_dphyrx", "clk_vio0_noc";
|
|
|
|
pinctrl-names =
|
|
"default", "isp_dvp8bit2", "isp_dvp10bit",
|
|
"isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
|
|
"isp_mipi_fl", "isp_mipi_fl_prefl",
|
|
"isp_flash_as_gpio", "isp_flash_as_trigger_out";
|
|
pinctrl-0 = <&cif_clkout>;
|
|
pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
|
|
pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
|
|
pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
|
|
pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
|
|
pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
|
|
pinctrl-6 = <&cif_clkout>;
|
|
pinctrl-7 = <&cif_clkout &isp_prelight>;
|
|
pinctrl-8 = <&isp_flash_trigger_as_gpio>;
|
|
pinctrl-9 = <&isp_flash_trigger>;
|
|
rockchip,isp,mipiphy = <2>;
|
|
rockchip,isp,cifphy = <1>;
|
|
rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
|
|
rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
|
|
rockchip,grf = <&grf>;
|
|
rockchip,cru = <&cru>;
|
|
rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
|
|
rockchip,isp,iommu-enable = <1>;
|
|
iommus = <&isp_mmu>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rkisp1: rkisp1@ff910000 {
|
|
compatible = "rockchip,rk3368-rkisp1";
|
|
reg = <0x0 0xff910000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "isp_irq";
|
|
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
|
|
<&cru SCLK_ISP>, <&cru PCLK_ISP>;
|
|
clock-names = "aclk_isp", "hclk_isp",
|
|
"clk_isp", "pclk_isp";
|
|
devfreq = <&dmc>;
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
iommus = <&isp_mmu>;
|
|
status = "disabled";
|
|
};
|
|
|
|
isp_mmu: iommu@ff914000 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff914000 0x0 0x100>,
|
|
<0x0 0xff915000 0x0 0x100>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "isp_mmu";
|
|
clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
|
|
clock-names = "aclk", "iface";
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
rockchip,disable-mmu-reset;
|
|
status = "disabled";
|
|
};
|
|
|
|
vop: vop@ff930000 {
|
|
compatible = "rockchip,rk3368-vop";
|
|
rockchip,grf = <&grf>;
|
|
reg = <0x0 0xff930000 0x0 0x2fc>, <0x0 0xff931000 0x0 0x400>;
|
|
reg-names = "regs", "gamma_lut";
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
|
|
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
|
|
assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
assigned-clock-rates = <400000000>, <200000000>;
|
|
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
|
|
reset-names = "axi", "ahb", "dclk";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
iommus = <&vop_mmu>;
|
|
status = "disabled";
|
|
|
|
vop_out: port {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
vop_out_dsi: endpoint@0 {
|
|
reg = <0>;
|
|
remote-endpoint = <&dsi_in_vop>;
|
|
};
|
|
|
|
vop_out_edp: endpoint@1 {
|
|
reg = <1>;
|
|
remote-endpoint = <&edp_in_vop>;
|
|
};
|
|
|
|
vop_out_hdmi: endpoint@2 {
|
|
reg = <2>;
|
|
remote-endpoint = <&hdmi_in_vop>;
|
|
};
|
|
|
|
vop_out_lvds: endpoint@3 {
|
|
reg = <3>;
|
|
remote-endpoint = <&lvds_in_vop>;
|
|
};
|
|
|
|
vop_out_rgb: endpoint@4 {
|
|
reg = <4>;
|
|
remote-endpoint = <&rgb_in_vop>;
|
|
};
|
|
};
|
|
};
|
|
|
|
display_subsystem: display-subsystem {
|
|
compatible = "rockchip,display-subsystem";
|
|
ports = <&vop_out>;
|
|
devfreq = <&dmc>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vop_mmu: iommu@ff930300 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff930300 0x0 0x100>;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vop_mmu";
|
|
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cif: cif@ff950000 {
|
|
compatible = "rockchip,cif";
|
|
reg = <0x0 0xff950000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_VIP>, <&cru ACLK_VIP>, <&cru HCLK_VIP>,
|
|
<&cru SCLK_VIP_SRC>, <&cru SCLK_VIP_OUT>;
|
|
clock-names = "pclk_cif", "aclk_cif0", "hclk_cif0",
|
|
"cif0_in", "cif0_out";
|
|
resets = <&cru SRST_VIP>;
|
|
reset-names = "rst_cif";
|
|
pinctrl-names = "cif_pin_all";
|
|
pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
|
|
rockchip,grf = <&grf>;
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
iommus = <&vip_mmu>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cif_new: cif-new@ff950000 {
|
|
compatible = "rockchip,rk3368-cif";
|
|
reg = <0x0 0xff950000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_VIP>, <&cru ACLK_VIP>, <&cru HCLK_VIP>,
|
|
<&cru SCLK_VIP_SRC>, <&cru SCLK_VIP_OUT>;
|
|
clock-names = "pclk_cif", "aclk_cif0", "hclk_cif0",
|
|
"cif0_in", "cif0_out";
|
|
resets = <&cru SRST_VIP>;
|
|
reset-names = "rst_cif";
|
|
rockchip,grf = <&grf>;
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
iommus = <&vip_mmu>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vip_mmu: iommu@ff950800{
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff950800 0x0 0x100>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vip_mmu";
|
|
clocks = <&cru ACLK_VIP>, <&cru HCLK_VIP>;
|
|
clock-names = "aclk", "hclk";
|
|
rk_iommu,disable_reset_quirk;
|
|
#iommu-cells = <0>;
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi: dsi@ff960000 {
|
|
compatible = "rockchip,rk3368-mipi-dsi";
|
|
reg = <0x0 0xff960000 0x0 0x4000>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_MIPI_DSI0>, <&video_phy>;
|
|
clock-names = "pclk", "hs_clk";
|
|
resets = <&cru SRST_MIPIDSI0>;
|
|
reset-names = "apb";
|
|
phys = <&video_phy>;
|
|
phy-names = "mipi_dphy";
|
|
rockchip,grf = <&grf>;
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
port {
|
|
dsi_in_vop: endpoint {
|
|
remote-endpoint = <&vop_out_dsi>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
video_phy: video-phy@ff968000 {
|
|
compatible = "rockchip,rk3368-video-phy";
|
|
reg = <0x0 0xff968000 0x0 0x4000>,
|
|
<0x0 0xff960000 0x0 0x4000>;
|
|
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>,
|
|
<&cru PCLK_MIPI_DSI0>;
|
|
clock-names = "ref", "pclk_phy", "pclk_host";
|
|
#clock-cells = <0>;
|
|
resets = <&cru SRST_MIPIDPHYTX>;
|
|
reset-names = "rst";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mipi_dphy_rx0: mipi-dphy-rx0@ff96C000 {
|
|
compatible = "rockchip,rk3368-mipi-dphy";
|
|
reg = <0x0 0xff96C000 0x0 0x4000>;
|
|
clocks = <&cru PCLK_DPHYRX>;
|
|
clock-names = "pclk_dphyrx";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
edp: edp@ff970000 {
|
|
compatible = "rockchip,rk3368-edp";
|
|
reg = <0x0 0xff970000 0x0 0x8000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
|
|
clock-names = "dp", "pclk";
|
|
assigned-clocks = <&cru SCLK_EDP_24M>;
|
|
assigned-clock-parents = <&xin24m>;
|
|
resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
|
|
reset-names = "dp", "apb";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
edp_in_vop: endpoint {
|
|
remote-endpoint = <&vop_out_edp>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
hdmi: hdmi@ff980000 {
|
|
compatible = "rockchip,rk3368-dw-hdmi";
|
|
reg = <0x0 0xff980000 0x0 0x20000>;
|
|
reg-io-width = <4>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hdmi", "hdmi_wakeup";
|
|
clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
|
|
clock-names = "iahb", "isfr", "cec";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
|
|
resets = <&cru SRST_HDMI>;
|
|
reset-names = "hdmi";
|
|
power-domains = <&power RK3368_PD_VIO>;
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
port {
|
|
hdmi_in_vop: endpoint {
|
|
remote-endpoint = <&vop_out_hdmi>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
mpp_srv: mpp-srv {
|
|
compatible = "rockchip,mpp-service";
|
|
rockchip,taskqueue-count = <1>;
|
|
rockchip,resetgroup-count = <1>;
|
|
rockchip,grf = <&grf>;
|
|
rockchip,grf-offset = <0x0418>;
|
|
rockchip,grf-values = <0x10001000>, <0x10000000>, <0x10000000>;
|
|
rockchip,grf-names = "grf_rkvdec", "grf_vdpu1", "grf_vepu1";
|
|
status = "disabled";
|
|
};
|
|
|
|
hevc: hevc_service@ff9a0000 {
|
|
compatible = "rockchip,hevc-decoder-rk3368";
|
|
reg = <0x0 0xff9a0000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_dec";
|
|
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
|
|
<&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
|
|
"clk_cabac";
|
|
rockchip,normal-rates = <300000000>, <0>, <200000000>,
|
|
<200000000>;
|
|
rockchip,advanced-rates = <500000000>, <0>, <400000000>,
|
|
<400000000>;
|
|
resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
|
|
<&cru SRST_VIDEO>;
|
|
reset-names = "shared_video_a", "shared_video_h", "video_core";
|
|
iommus = <&hevc_mmu>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,taskqueue-node = <0>;
|
|
rockchip,resetgroup-node = <0>;
|
|
power-domains = <&power RK3368_PD_VIDEO>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vepu: vepu@ff9a0000 {
|
|
compatible = "rockchip,vpu-encoder-v1";
|
|
reg = <0x0 0xff9a0000 0x0 0x400>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_enc";
|
|
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>;
|
|
reset-names = "shared_video_a", "shared_video_h";
|
|
iommus = <&vpu_mmu>;
|
|
power-domains = <&power RK3368_PD_VIDEO>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,taskqueue-node = <0>;
|
|
rockchip,resetgroup-node = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vdpu: vdpu@ff9a0400 {
|
|
compatible = "rockchip,vpu-decoder-rk3368";
|
|
reg = <0x0 0xff9a0400 0x0 0x400>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "irq_dec";
|
|
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
|
|
clock-names = "aclk_vcodec", "hclk_vcodec";
|
|
rockchip,normal-rates = <300000000>, <0>;
|
|
rockchip,advanced-rates = <600000000>, <0>;
|
|
resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>;
|
|
reset-names = "shared_video_a", "shared_video_h";
|
|
iommus = <&vpu_mmu>;
|
|
power-domains = <&power RK3368_PD_VIDEO>;
|
|
rockchip,srv = <&mpp_srv>;
|
|
rockchip,taskqueue-node = <0>;
|
|
rockchip,resetgroup-node = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hevc_mmu: iommu@ff9a0440 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff9a0440 0x0 0x40>,
|
|
<0x0 0xff9a0480 0x0 0x40>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hevc_mmu";
|
|
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3368_PD_VIDEO>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vpu_mmu: iommu@ff9a0800 {
|
|
compatible = "rockchip,iommu";
|
|
reg = <0x0 0xff9a0800 0x0 0x100>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "vepu_mmu", "vdpu_mmu";
|
|
clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
|
|
clock-names = "aclk", "iface";
|
|
power-domains = <&power RK3368_PD_VIDEO>;
|
|
#iommu-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@ffb71000 {
|
|
compatible = "arm,gic-400";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
|
|
reg = <0x0 0xffb71000 0x0 0x1000>,
|
|
<0x0 0xffb72000 0x0 0x2000>,
|
|
<0x0 0xffb74000 0x0 0x2000>,
|
|
<0x0 0xffb76000 0x0 0x2000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
gpu: rogue-g6110@ffa30000 {
|
|
compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
|
|
reg = <0x0 0xffa30000 0x0 0x10000>;
|
|
clocks =
|
|
<&cru SCLK_GPU_CORE>,
|
|
<&cru ACLK_GPU_MEM>,
|
|
<&cru ACLK_GPU_CFG>;
|
|
clock-names =
|
|
"sclk_gpu_core",
|
|
"aclk_gpu_mem",
|
|
"aclk_gpu_cfg";
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "rogue-g6110-irq";
|
|
power-domains = <&power RK3368_PD_GPU_1>;
|
|
operating-points-v2 = <&gpu_opp_table>;
|
|
#cooling-cells = <2>; /* min followed by max */
|
|
gpu_power_model: power_model {
|
|
compatible = "arm,mali-simple-power-model";
|
|
voltage = <900>;
|
|
frequency = <500>;
|
|
static-power = <300>;
|
|
dynamic-power = <396>;
|
|
ts = <32000 4700 (-80) 2>;
|
|
thermal-zone = "gpu-thermal";
|
|
};
|
|
};
|
|
|
|
gpu_opp_table: gpu_opp_table {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
|
|
opp-200000000 {
|
|
opp-hz = /bits/ 64 <200000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
opp-288000000 {
|
|
opp-hz = /bits/ 64 <288000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
opp-400000000 {
|
|
opp-hz = /bits/ 64 <400000000>;
|
|
opp-microvolt = <1100000>;
|
|
};
|
|
opp-576000000 {
|
|
opp-hz = /bits/ 64 <576000000>;
|
|
opp-microvolt = <1200000>;
|
|
};
|
|
};
|
|
|
|
nocp_peri: nocp-peri@ffac1000 {
|
|
compatible = "rockchip,rk3368-nocp";
|
|
reg = <0x0 0xffac1000 0x0 0x400>;
|
|
};
|
|
|
|
nocp_core: nocp-core@ffac1400 {
|
|
compatible = "rockchip,rk3368-nocp";
|
|
reg = <0x0 0xffac1400 0x0 0x400>;
|
|
};
|
|
|
|
nocp_gpu: nocp-gpu@ffac1800 {
|
|
compatible = "rockchip,rk3368-nocp";
|
|
reg = <0x0 0xffac1800 0x0 0x400>;
|
|
};
|
|
|
|
nocp_vpu: nocp-vpu@ffac2000 {
|
|
compatible = "rockchip,rk3368-nocp";
|
|
reg = <0x0 0xffac2000 0x0 0x400>;
|
|
};
|
|
|
|
nocp_vop: nocp-vop@ffac2400 {
|
|
compatible = "rockchip,rk3368-nocp";
|
|
reg = <0x0 0xffac2400 0x0 0x400>;
|
|
};
|
|
|
|
nocp_rga: nocp-rga@ffac2800 {
|
|
compatible = "rockchip,rk3368-nocp";
|
|
reg = <0x0 0xffac2800 0x0 0x400>;
|
|
};
|
|
|
|
efuse: efuse@ffb00000 {
|
|
compatible = "rockchip,rk3368-efuse";
|
|
reg = <0x0 0xffb00000 0x0 0x20>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&cru PCLK_EFUSE256>;
|
|
clock-names = "pclk_efuse";
|
|
|
|
/* Data cells */
|
|
cpu_leakage: cpu-leakage@17 {
|
|
reg = <0x17 0x1>;
|
|
};
|
|
leakage_volt: leakage-volt@1a {
|
|
reg = <0x1a 0x1>;
|
|
bits = <7 1>;
|
|
};
|
|
leakage_temp: leakage-temp@1e {
|
|
reg = <0x1e 0x1>;
|
|
bits = <1 7>;
|
|
};
|
|
temp_adjust: temp-adjust@1f {
|
|
reg = <0x1f 0x1>;
|
|
};
|
|
};
|
|
|
|
rockchip_system_monitor: rockchip-system-monitor {
|
|
compatible = "rockchip,system-monitor";
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3368-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
rockchip,pmu = <&pmugrf>;
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x2>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@ff750000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff750000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio1: gpio1@ff780000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff780000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio2: gpio2@ff790000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff790000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
gpio3: gpio3@ff7a0000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x0 0xff7a0000 0x0 0x100>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <0x2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <0x2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_12ma: pcfg-pull-none-12ma {
|
|
bias-disable;
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
edp {
|
|
edp_hpd: edp-hpd {
|
|
rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_pwr: emmc-pwr {
|
|
rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus1: emmc-bus1 {
|
|
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus4: emmc-bus4 {
|
|
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
|
|
<1 RK_PC3 2 &pcfg_pull_up>,
|
|
<1 RK_PC4 2 &pcfg_pull_up>,
|
|
<1 RK_PC5 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
|
|
<1 RK_PC3 2 &pcfg_pull_up>,
|
|
<1 RK_PC4 2 &pcfg_pull_up>,
|
|
<1 RK_PC5 2 &pcfg_pull_up>,
|
|
<1 RK_PC6 2 &pcfg_pull_up>,
|
|
<1 RK_PC7 2 &pcfg_pull_up>,
|
|
<1 RK_PD0 2 &pcfg_pull_up>,
|
|
<1 RK_PD1 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rgmii_pins: rgmii-pins {
|
|
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
|
|
<3 RK_PD0 1 &pcfg_pull_none>,
|
|
<3 RK_PC3 1 &pcfg_pull_none>,
|
|
<3 RK_PB0 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB1 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB2 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB6 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PD4 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB5 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB7 1 &pcfg_pull_none>,
|
|
<3 RK_PC0 1 &pcfg_pull_none>,
|
|
<3 RK_PC1 1 &pcfg_pull_none>,
|
|
<3 RK_PC2 1 &pcfg_pull_none>,
|
|
<3 RK_PD1 1 &pcfg_pull_none>,
|
|
<3 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
|
|
<3 RK_PD0 1 &pcfg_pull_none>,
|
|
<3 RK_PC3 1 &pcfg_pull_none>,
|
|
<3 RK_PB0 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB1 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB5 1 &pcfg_pull_none_12ma>,
|
|
<3 RK_PB7 1 &pcfg_pull_none>,
|
|
<3 RK_PC0 1 &pcfg_pull_none>,
|
|
<3 RK_PC4 1 &pcfg_pull_none>,
|
|
<3 RK_PC5 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
hdmi {
|
|
hdmi_cec: hdmi-cec {
|
|
rockchip,pins = <3 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
hdmi_i2c_xfer: hdmi-i2c-xfer {
|
|
rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>,
|
|
<3 RK_PD3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
|
|
<0 RK_PA7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
|
|
<2 RK_PC6 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
|
|
<3 RK_PD7 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
|
|
<1 RK_PC1 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c4 {
|
|
i2c4_xfer: i2c4-xfer {
|
|
rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
|
|
<3 RK_PD1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c5 {
|
|
i2c5_xfer: i2c5-xfer {
|
|
rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
|
|
<3 RK_PD3 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s {
|
|
i2s_8ch_bus: i2s-8ch-bus {
|
|
rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
|
|
<2 RK_PB5 1 &pcfg_pull_none>,
|
|
<2 RK_PB6 1 &pcfg_pull_none>,
|
|
<2 RK_PB7 1 &pcfg_pull_none>,
|
|
<2 RK_PC0 1 &pcfg_pull_none>,
|
|
<2 RK_PC1 1 &pcfg_pull_none>,
|
|
<2 RK_PC2 1 &pcfg_pull_none>,
|
|
<2 RK_PC3 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
i2s_8ch_mclk: i2s-8ch-mclk {
|
|
rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm0_pin_pull_down: pwm0-pin-pull-down {
|
|
rockchip,pins = <3 RK_PB0 2 &pcfg_pull_down>;
|
|
};
|
|
|
|
vop_pwm_pin: vop-pwm {
|
|
rockchip,pins = <3 RK_PB0 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm1_pin_pull_down: pwm1-pin-pull-down {
|
|
rockchip,pins = <0 RK_PB0 2 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
pwm3_pin_pull_down: pwm3-pin-pull-down {
|
|
rockchip,pins = <3 RK_PD6 3 &pcfg_pull_down>;
|
|
};
|
|
};
|
|
|
|
sdio0 {
|
|
sdio0_bus1: sdio0-bus1 {
|
|
rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bus4: sdio0-bus4 {
|
|
rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
|
|
<2 RK_PD5 1 &pcfg_pull_up>,
|
|
<2 RK_PD6 1 &pcfg_pull_up>,
|
|
<2 RK_PD7 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_cmd: sdio0-cmd {
|
|
rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_clk: sdio0-clk {
|
|
rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdio0_cd: sdio0-cd {
|
|
rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_wp: sdio0-wp {
|
|
rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_pwr: sdio0-pwr {
|
|
rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_bkpwr: sdio0-bkpwr {
|
|
rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdio0_int: sdio0-int {
|
|
rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_cd: sdmmc-cd {
|
|
rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus1: sdmmc-bus1 {
|
|
rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
|
|
<2 RK_PA6 1 &pcfg_pull_up>,
|
|
<2 RK_PA7 1 &pcfg_pull_up>,
|
|
<2 RK_PB0 1 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spdif {
|
|
spdif_bus: spdif-bus {
|
|
rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
spi0_clk: spi0-clk {
|
|
rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs0: spi0-cs0 {
|
|
rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
|
|
};
|
|
spi0_cs1: spi0-cs1 {
|
|
rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
|
|
};
|
|
spi0_tx: spi0-tx {
|
|
rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
|
|
};
|
|
spi0_rx: spi0-rx {
|
|
rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
spi1_clk: spi1-clk {
|
|
rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs0: spi1-cs0 {
|
|
rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
|
|
};
|
|
spi1_cs1: spi1-cs1 {
|
|
rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
|
|
};
|
|
spi1_rx: spi1-rx {
|
|
rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
|
|
};
|
|
spi1_tx: spi1-tx {
|
|
rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
spi2 {
|
|
spi2_clk: spi2-clk {
|
|
rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
|
|
};
|
|
spi2_cs0: spi2-cs0 {
|
|
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
|
|
};
|
|
spi2_rx: spi2-rx {
|
|
rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
|
|
};
|
|
spi2_tx: spi2-tx {
|
|
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
|
|
<2 RK_PD1 1 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
|
|
<0 RK_PC5 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
|
|
<2 RK_PA5 2 &pcfg_pull_up>;
|
|
};
|
|
/* no rts / cts for uart2 */
|
|
};
|
|
|
|
uart3 {
|
|
uart3_xfer: uart3-xfer {
|
|
rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
|
|
<3 RK_PD6 2 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart3_cts: uart3-cts {
|
|
rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart3_rts: uart3-rts {
|
|
rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart4 {
|
|
uart4_xfer: uart4-xfer {
|
|
rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
|
|
<0 RK_PD2 3 &pcfg_pull_up>;
|
|
};
|
|
|
|
uart4_cts: uart4-cts {
|
|
rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart4_rts: uart4-rts {
|
|
rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
isp {
|
|
cif_clkout: cif-clkout {
|
|
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
|
|
};
|
|
|
|
isp_dvp_d2d9: isp-dvp-d2d9 {
|
|
rockchip,pins =
|
|
<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
|
|
<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
|
|
<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
|
|
<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
|
|
<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
|
|
<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
|
|
<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
|
|
<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
|
|
<1 RK_PB0 1 &pcfg_pull_none>,//cif_sync
|
|
<1 RK_PB1 1 &pcfg_pull_none>,//cif_href
|
|
<1 RK_PB2 1 &pcfg_pull_none>,//cif_clkin
|
|
<1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout
|
|
};
|
|
|
|
isp_dvp_d0d1: isp-dvp-d0d1 {
|
|
rockchip,pins =
|
|
<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
|
|
<1 RK_PB5 1 &pcfg_pull_none>;//cif_data1
|
|
};
|
|
|
|
isp_dvp_d10d11:isp_d10d11 {
|
|
rockchip,pins =
|
|
<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
|
|
<1 RK_PB7 1 &pcfg_pull_none>;//cif_data11
|
|
};
|
|
|
|
isp_dvp_d0d7: isp-dvp-d0d7 {
|
|
rockchip,pins =
|
|
<1 RK_PB4 1 &pcfg_pull_none>,//cif_data0
|
|
<1 RK_PB5 1 &pcfg_pull_none>,//cif_data1
|
|
<1 RK_PA0 1 &pcfg_pull_none>,//cif_data2
|
|
<1 RK_PA1 1 &pcfg_pull_none>,//cif_data3
|
|
<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
|
|
<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
|
|
<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
|
|
<1 RK_PA5 1 &pcfg_pull_none>;//cif_data7
|
|
};
|
|
|
|
isp_dvp_d4d11: isp-dvp-d4d11 {
|
|
rockchip,pins =
|
|
<1 RK_PA2 1 &pcfg_pull_none>,//cif_data4
|
|
<1 RK_PA3 1 &pcfg_pull_none>,//cif_data5
|
|
<1 RK_PA4 1 &pcfg_pull_none>,//cif_data6
|
|
<1 RK_PA5 1 &pcfg_pull_none>,//cif_data7
|
|
<1 RK_PA6 1 &pcfg_pull_none>,//cif_data8
|
|
<1 RK_PA7 1 &pcfg_pull_none>,//cif_data9
|
|
<1 RK_PB6 1 &pcfg_pull_none>,//cif_data10
|
|
<1 RK_PC1 1 &pcfg_pull_none>;//cif_data11
|
|
};
|
|
|
|
isp_shutter: isp-shutter {
|
|
rockchip,pins =
|
|
<3 RK_PC3 2 &pcfg_pull_none>, //SHUTTEREN
|
|
<3 RK_PC6 2 &pcfg_pull_none>;//SHUTTERTRIG
|
|
};
|
|
|
|
isp_flash_trigger: isp-flash-trigger {
|
|
rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
|
|
};
|
|
|
|
isp_prelight: isp-prelight {
|
|
rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
|
|
};
|
|
|
|
isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
|
|
rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
|
|
};
|
|
};
|
|
|
|
lcdc {
|
|
lcdc_rgb_pins: lcdc-rgb-pins {
|
|
rockchip,pins =
|
|
<0 RK_PB6 1 &pcfg_pull_none>, /* LCDC_D10 */
|
|
<0 RK_PB7 1 &pcfg_pull_none>, /* LCDC_D11 */
|
|
<0 RK_PC0 1 &pcfg_pull_none>, /* LCDC_D12 */
|
|
<0 RK_PC1 1 &pcfg_pull_none>, /* LCDC_D13 */
|
|
<0 RK_PC2 1 &pcfg_pull_none>, /* LCDC_D14 */
|
|
<0 RK_PC3 1 &pcfg_pull_none>, /* LCDC_D15 */
|
|
<0 RK_PC4 1 &pcfg_pull_none>, /* LCDC_D16 */
|
|
<0 RK_PC5 1 &pcfg_pull_none>, /* LCDC_D17 */
|
|
<0 RK_PC6 1 &pcfg_pull_none>, /* LCDC_D18 */
|
|
<0 RK_PC7 1 &pcfg_pull_none>, /* LCDC_D19 */
|
|
<0 RK_PD0 1 &pcfg_pull_none>, /* LCDC_D20 */
|
|
<0 RK_PD1 1 &pcfg_pull_none>, /* LCDC_D21 */
|
|
<0 RK_PD2 1 &pcfg_pull_none>, /* LCDC_D22 */
|
|
<0 RK_PD3 1 &pcfg_pull_none>, /* LCDC_D23 */
|
|
<0 RK_PD7 1 &pcfg_pull_none>, /* DCLK */
|
|
<0 RK_PD6 1 &pcfg_pull_none>, /* DEN */
|
|
<0 RK_PD4 1 &pcfg_pull_none>, /* HSYNC */
|
|
<0 RK_PD5 1 &pcfg_pull_none>; /* VSYNC */
|
|
};
|
|
|
|
lcdc_sleep_pins: lcdc-sleep-pins {
|
|
rockchip,pins =
|
|
<0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
|
|
<0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
|
|
<0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
|
|
<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
|
|
<0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
|
|
<0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
|
|
<0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
|
|
<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
|
|
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
|
|
<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
|
|
<0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
|
|
<0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
|
|
<0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
|
|
<0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
|
|
<0 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>, /* DCLK */
|
|
<0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
|
|
<0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
|
|
<0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; /* VSYNC */
|
|
};
|
|
};
|
|
};
|
|
|
|
rockchip_suspend: rockchip-suspend {
|
|
compatible = "rockchip,pm-rk3368";
|
|
status = "disabled";
|
|
rockchip,sleep-debug-en = <0>;
|
|
rockchip,sleep-mode-config = <
|
|
(0
|
|
| RKPM_SLP_ARMOFF
|
|
| RKPM_SLP_PMU_PLLS_PWRDN
|
|
| RKPM_SLP_PMU_PMUALIVE_32K
|
|
| RKPM_SLP_SFT_PLLS_DEEP
|
|
| RKPM_SLP_PMU_DIS_OSC
|
|
| RKPM_SLP_SFT_PD_NBSCUS
|
|
)
|
|
>;
|
|
rockchip,wakeup-config = <
|
|
(0
|
|
| RKPM_GPIO_WKUP_EN
|
|
| RKPM_USB_WKUP_EN
|
|
)
|
|
>;
|
|
};
|
|
};
|