262 lines
6.8 KiB
C
262 lines
6.8 KiB
C
/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Chris Zhong <zyw@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/bug.h> /* BUILD_BUG_ON */
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#include <linux/kernel.h>
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#include <asm/io.h>
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#include "rk3288_ddr.h"
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#include "rk3288_resume.h"
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#include "sram_delay.h"
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#include "../pm.h"
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#define PMU_ADDR 0xff730000
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#define PMU_PWRMODE_CON_ADDR ((void *)(PMU_ADDR + RK3288_PMU_PWRMODE_CON))
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#define DDR_PCTRL0_ADDR ((void *)0xff610000)
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#define DDR_PUBL0_ADDR ((void *)0xff620000) /* phy */
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#define DDR_PCTRL1_ADDR ((void *)0xff630000)
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#define DDR_PUBL1_ADDR ((void *)0xff640000) /* phy */
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#define MSCH0_ADDR ((void *)0xffac0000)
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#define MSCH1_ADDR ((void *)0xffac0080)
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static void * const pctrl_addrs[] = { DDR_PCTRL0_ADDR, DDR_PCTRL1_ADDR };
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static void * const phy_addrs[] = { DDR_PUBL0_ADDR, DDR_PUBL1_ADDR };
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static void * const msch_addrs[] = { MSCH0_ADDR, MSCH1_ADDR };
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static void reset_dll(void __iomem *phy_addr)
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{
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static const u32 reg[] = { DDR_PUBL_ACDLLCR, DDR_PUBL_DX0DLLCR,
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DDR_PUBL_DX1DLLCR, DDR_PUBL_DX2DLLCR,
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DDR_PUBL_DX3DLLCR };
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int i;
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for (i = 0; i < ARRAY_SIZE(reg); i++)
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writel_relaxed(readl_relaxed(phy_addr + reg[i]) & ~DLLSRST,
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phy_addr + reg[i]);
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sram_udelay(10);
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for (i = 0; i < ARRAY_SIZE(reg); i++)
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writel_relaxed(readl_relaxed(phy_addr + reg[i]) | DLLSRST,
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phy_addr + reg[i]);
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sram_udelay(10);
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}
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static void phy_init(void __iomem *phy_addr)
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{
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u32 val;
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val = readl_relaxed(phy_addr + DDR_PUBL_PIR);
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val |= PIR_INIT | PIR_DLLSRST | PIR_DLLLOCK |
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PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR;
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writel_relaxed(val, phy_addr + DDR_PUBL_PIR);
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sram_udelay(1);
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while ((readl_relaxed(phy_addr + DDR_PUBL_PGSR) &
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(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) !=
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(PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE))
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;
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}
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static void memory_init(void __iomem *phy_addr)
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{
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u32 val;
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val = readl_relaxed(phy_addr + DDR_PUBL_PIR);
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val |= PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP |
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PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC;
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writel_relaxed(val, phy_addr + DDR_PUBL_PIR);
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sram_udelay(1);
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while ((readl_relaxed(phy_addr + DDR_PUBL_PGSR) &
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(PGSR_IDONE | PGSR_DLDONE)) != (PGSR_IDONE | PGSR_DLDONE))
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;
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}
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static void move_to_lowpower_state(void __iomem *pctrl_addr,
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void __iomem *phy_addr)
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{
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u32 state;
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while (1) {
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state = readl_relaxed(pctrl_addr +
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DDR_PCTL_STAT) & PCTL_STAT_MSK;
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switch (state) {
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case INIT_MEM:
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writel_relaxed(CFG_STATE, pctrl_addr + DDR_PCTL_SCTL);
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while ((readl_relaxed(pctrl_addr + DDR_PCTL_STAT) &
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PCTL_STAT_MSK) != CONFIG)
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;
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/* no break */
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case CONFIG:
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writel_relaxed(GO_STATE, pctrl_addr + DDR_PCTL_SCTL);
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while ((readl_relaxed(pctrl_addr + DDR_PCTL_STAT) &
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PCTL_STAT_MSK) != ACCESS)
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;
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/* no break */
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case ACCESS:
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writel_relaxed(SLEEP_STATE, pctrl_addr + DDR_PCTL_SCTL);
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while ((readl_relaxed(pctrl_addr + DDR_PCTL_STAT) &
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PCTL_STAT_MSK) != LOW_POWER)
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;
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/* no break */
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case LOW_POWER:
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return;
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default:
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break;
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}
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}
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}
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static void move_to_access_state(void __iomem *pctrl_addr,
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void __iomem *phy_addr)
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{
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u32 state;
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while (1) {
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state = readl_relaxed(pctrl_addr +
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DDR_PCTL_STAT) & PCTL_STAT_MSK;
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switch (state) {
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case LOW_POWER:
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if (LP_TRIG_VAL(readl_relaxed(pctrl_addr +
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DDR_PCTL_STAT)) == 1)
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return;
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writel_relaxed(WAKEUP_STATE,
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pctrl_addr + DDR_PCTL_SCTL);
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while ((readl_relaxed(pctrl_addr + DDR_PCTL_STAT) &
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PCTL_STAT_MSK) != ACCESS)
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;
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/* wait DLL lock */
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while ((readl_relaxed(phy_addr +
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DDR_PUBL_PGSR) & PGSR_DLDONE)
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!= PGSR_DLDONE)
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;
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break;
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case INIT_MEM:
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writel_relaxed(CFG_STATE, pctrl_addr + DDR_PCTL_SCTL);
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while ((readl_relaxed(pctrl_addr + DDR_PCTL_STAT) &
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PCTL_STAT_MSK) != CONFIG)
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;
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/* fallthrough here */
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case CONFIG:
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writel_relaxed(GO_STATE, pctrl_addr + DDR_PCTL_SCTL);
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while ((readl_relaxed(pctrl_addr + DDR_PCTL_STAT) &
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PCTL_STAT_MSK) == CONFIG)
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;
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break;
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case ACCESS:
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return;
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default:
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break;
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}
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}
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}
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static void rk3288_ddr_reg_restore(void __iomem *regbase, const u32 reg_list[],
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int num_reg, const u32 *vals)
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{
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int i;
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for (i = 0; i < num_reg && reg_list[i] != RK3288_BOGUS_OFFSET; i++)
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writel_relaxed(vals[i], regbase + reg_list[i]);
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}
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void rk3288_ddr_resume_early(const struct rk3288_ddr_save_data *ddr_save_data)
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{
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int ch;
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/* PWM saves full address, so base is NULL */
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rk3288_ddr_reg_restore(NULL, ddr_save_data->pwm_addrs,
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RK3288_MAX_PWM_REGS, ddr_save_data->pwm_vals);
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/*
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* PWM never runs higher than 1.2V giving a 2000uV/us ramp delay since
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* we start from 1V. This is a very conservative ramp delay for the
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* regulator.
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*/
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sram_udelay(100);
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for (ch = 0; ch < ARRAY_SIZE(pctrl_addrs); ch++) {
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/* DLL bypass */
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rk3288_ddr_reg_restore(phy_addrs[ch],
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ddr_save_data->phy_dll_offsets,
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RK3288_MAX_DDR_PHY_DLL_REGS,
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ddr_save_data->phy_dll_vals[ch]);
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reset_dll(phy_addrs[ch]);
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/* ddr ctrl restore; NOTE: both channels must be the same */
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rk3288_ddr_reg_restore(pctrl_addrs[ch],
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ddr_save_data->ctrl_offsets,
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RK3288_MAX_DDR_CTRL_REGS,
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ddr_save_data->ctrl_vals);
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/* ddr phy restore */
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rk3288_ddr_reg_restore(phy_addrs[ch],
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ddr_save_data->phy_offsets,
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RK3288_MAX_DDR_PHY_REGS,
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ddr_save_data->phy_vals[ch]);
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/* msch restore */
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rk3288_ddr_reg_restore(msch_addrs[ch],
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ddr_save_data->msch_offsets,
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RK3288_MAX_DDR_MSCH_REGS,
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ddr_save_data->msch_vals[ch]);
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phy_init(phy_addrs[ch]);
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/* power up ddr power */
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writel_relaxed(POWER_UP_START,
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pctrl_addrs[ch] + DDR_PCTL_POWCTL);
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while (!(readl_relaxed(pctrl_addrs[ch] + DDR_PCTL_POWSTAT) &
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POWER_UP_DONE))
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;
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/* zqcr restore; NOTE: both channels must be the same */
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rk3288_ddr_reg_restore(phy_addrs[ch],
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ddr_save_data->phy_zqcr_offsets,
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RK3288_MAX_DDR_PHY_ZQCR_REGS,
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ddr_save_data->phy_zqcr_vals);
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memory_init(phy_addrs[ch]);
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move_to_lowpower_state(pctrl_addrs[ch], phy_addrs[ch]);
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}
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/* disable retention */
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writel_relaxed(readl_relaxed(PMU_PWRMODE_CON_ADDR) |
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DDR0IO_RET_DE_REQ | DDR0I1_RET_DE_REQ,
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PMU_PWRMODE_CON_ADDR);
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sram_udelay(1);
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/* disable self-refresh */
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for (ch = 0; ch < ARRAY_SIZE(pctrl_addrs); ch++)
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move_to_access_state(pctrl_addrs[ch], phy_addrs[ch]);
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}
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