199 lines
5.4 KiB
C
199 lines
5.4 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _TRX_TEST_H_
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#define _TRX_TEST_H_
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#ifdef CONFIG_PHL_TEST_SUITE
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#define MAX_TEST_TXREQ_NUM 256
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#define MAX_TEST_PAYLOAD_NUM MAX_TEST_TXREQ_NUM
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#define MAX_TEST_RXREQ_NUM 256
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#define MAX_TEST_PAYLOAD_SIZE 2308
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enum test_mode {
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TEST_MODE_PHL_TX_RING_TEST = 1,
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TEST_MODE_PHL_RX_RING_TEST = 2,
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TEST_MODE_PHL_RING_LOOPBACK = 3,
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TEST_MODE_PHL_PCIE_LOOPBACK = 4,
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TEST_MODE_HAL_TX_TEST = 5,
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TEST_MODE_HAL_RX_TEST = 6,
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TEST_MODE_HAL_WP_REPORT_PARSE = 7,
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TEST_MODE_HAL_RXDESC_PARSE = 8,
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TEST_MODE_HAL_RXBD_PARSE = 9
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};
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enum pkt_type {
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TEST_PKT_TYPE_UNI = 1,
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TEST_PKT_TYPE_MC = 2,
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TEST_PKT_TYPE_BC = 3,
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TEST_PKT_TYPE_MAX = 0xFF,
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};
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struct rtw_tx_cap {
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u16 macid;
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u8 tid;
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u8 wmm; /* for halmac add role */
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u8 dma_ch;
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u8 band;
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u8 force_txcap;
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u16 rate;
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u8 bw;
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u8 gi_ltf;
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u8 stbc;
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u8 ldpc;
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u8 bk;
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u8 type;
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};
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struct rtw_pool {
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u8 *buf;
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u32 buf_len;
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_os_list idle_list;
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_os_list busy_list;
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_os_lock idle_lock;
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_os_lock busy_lock;
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u32 total_cnt;
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u32 idle_cnt;
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u32 busy_cnt;
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};
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struct rtw_test_rx {
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_os_list list;
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u32 test_id;
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struct rtw_recv_pkt rx;
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u8 *tpkt; /* for loopback mode */
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};
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struct rtw_payload {
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_os_list list;
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u32 test_id;
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struct rtw_pkt_buf_list pkt;
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void *os_rsvd[1];
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};
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struct rtw_trx_test_param {
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u8 is_trx_test_end;
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u8 mode;
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/* parameter for trx resource*/
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u32 tx_req_num;
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u32 rx_req_num;
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u32 tx_payload_num;
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u32 tx_payload_size;
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enum pkt_type pkt_type;
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u8 ap_mode;
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u8 trx_mode;
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u8 qta_mode;
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u8 qos;
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u8 cur_addr[6]; /* mac address of this device */
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u8 sta_addr[6]; /* mac address of associating device */
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u8 bssid[6];
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/* parameter for tx capability */
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struct rtw_t_meta_data tx_cap;
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/* parameter for hw configure */
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/* misc */
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};
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struct phl_trx_test {
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_os_list rx_q;
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_os_lock rx_q_lock;
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struct rtw_pool tx_req_pool;
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struct rtw_pool rx_req_pool;
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struct rtw_pool tx_pkt_pool;
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struct test_obj_ctrl_interface trx_test_obj;
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struct rtw_trx_test_param test_param;
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struct rtw_phl_handler test_rxq_handler;
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};
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#define WHDR_OFST_FRAME_CONTROL 0
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#define WHDR_OFST_DURATION 2
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#define WHDR_OFST_ADDRESS1 4
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#define WHDR_OFST_ADDRESS2 10
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#define WHDR_OFST_ADDRESS3 16
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#define WHDR_OFST_SEQUENCE 22
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#define WHDR_OFST_ADDRESS4 24
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#define WHDR_QOS_LENGTH 2
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#define SET_WHDR_PROTOCOL_VERSION(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 0, 2, _val)
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#define SET_WHDR_TYPE(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 2, 2, _val)
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#define SET_WHDR_SUBTYPE(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 4, 4, _val)
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#define SET_WHDR_TO_DS(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
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#define SET_WHDR_FROM_DS(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 9, 1, _val)
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#define SET_WHDR_MORE_FRAG(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 10, 1, _val)
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#define SET_WHDR_RETRY(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 11, 1, _val)
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#define SET_WHDR_PWR_MGNT(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
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#define SET_WHDR_MORE_DATA(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 13, 1, _val)
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#define SET_WHDR_WEP(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 14, 1, _val)
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#define SET_WHDR_ORDER(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 15, 1, _val)
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#define SET_WHDR_QOS_EN(_hdr, _val) \
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SET_BITS_TO_LE_2BYTE(_hdr, 7, 1, _val)
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#define SET_WHDR_DURATION(_hdr, _val) \
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WriteLE2Byte(_hdr + WHDR_OFST_DURATION, _val)
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#define SET_WHDR_ADDRESS1(_drv, _hdr, _val) \
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_os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS1, _val, 6)
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#define SET_WHDR_ADDRESS2(_drv, _hdr, _val) \
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_os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS2, _val, 6)
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#define SET_WHDR_ADDRESS3(_drv, _hdr, _val) \
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_os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS3, _val, 6)
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#define SET_WHDR_FRAGMENT_SEQUENCE(_hdr, _val) \
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WriteLE2Byte(_hdr + WHDR_OFST_SEQUENCE, _val)
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#define SET_WHDR_ADDRESS4(_drv, _hdr, _val) \
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_os_mem_cpy(_drv, _hdr + WHDR_OFST_ADDRESS4, _val, 6)
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#define SET_WHDR_QOS_CTRL_STA_DATA_TID(_qos, _value) \
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SET_BITS_TO_LE_2BYTE((u8 *)_qos, 0, 4, (u8)(_value))
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#define SET_WHDR_QOS_CTRL_STA_DATA_EOSP(_qos, _value) \
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SET_BITS_TO_LE_2BYTE((u8 *)_qos, 4, 1, (u8)(_value))
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#define SET_WHDR_QOS_CTRL_STA_DATA_ACK_POLICY(_qos, _value) \
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SET_BITS_TO_LE_2BYTE((u8 *)_qos, 5, 2, (u8)(_value))
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#define SET_WHDR_QOS_CTRL_STA_DATA_AMSDU(_qos, _value) \
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SET_BITS_TO_LE_2BYTE((u8 *)_qos, 7, 1, (u8)(_value))
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#define SET_WHDR_QOS_CTRL_STA_DATA_TXOP(_qos, _value) \
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SET_BITS_TO_LE_1BYTE((u8 *)_qos + 1, 0, 8, (u8)(_value))
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enum rtw_phl_status phl_trx_test_init(void *phl);
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void phl_trx_test_deinit(void *phl);
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void rtw_phl_trx_default_param(void *phl,
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struct rtw_trx_test_param *test_param);
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enum rtw_phl_status rtw_phl_trx_testsuite(void *phl,
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struct rtw_trx_test_param *test_param);
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#else /*!CONFIG_PHL_TEST_SUITE*/
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#define phl_trx_test_init(phl)
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#define phl_trx_test_deinit(phl)
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#define rtw_phl_trx_default_param(phl, test_param)
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#define rtw_phl_trx_testsuite(phl, test_param) RTW_PHL_STATUS_SUCCESS
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#endif
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#endif /*_TRX_TEST_H_*/
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