800 lines
20 KiB
C
800 lines
20 KiB
C
/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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/*
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The purpose of hal_io.c
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a. provides the API
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b. provides the protocol engine
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c. provides the software interface between caller and the hardware interface
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Compiler Flag Option:
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1. CONFIG_SDIO_HCI:
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a. USE_SYNC_IRP: Only sync operations are provided.
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b. USE_ASYNC_IRP:Both sync/async operations are provided.
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2. CONFIG_USB_HCI:
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a. USE_ASYNC_IRP: Both sync/async operations are provided.
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3. CONFIG_CFIO_HCI:
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b. USE_SYNC_IRP: Only sync operations are provided.
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Only sync read/rtw_write_mem operations are provided.
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*/
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#define _HAL_IO_C_
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#include "hal_headers.h"
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u8 _hal_read8(struct rtw_hal_com_t *hal, u32 addr)
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{
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u8 r_val;
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struct hal_io_priv *io_priv = &hal->iopriv;
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u8(*_read8)(struct rtw_hal_com_t *hal, u32 addr);
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#ifdef DBG_PHL_MAC_REG_RW
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if (rtw_hal_mac_reg_chk(hal, addr) == false) {
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r_val = 0xEA;
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return r_val;
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}
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#endif
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_read8 = io_priv->io_ops._read8;
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r_val = _read8(hal, addr);
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return r_val;
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}
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u16 _hal_read16(struct rtw_hal_com_t *hal, u32 addr)
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{
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u16 r_val;
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struct hal_io_priv *io_priv = &hal->iopriv;
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u16(*_read16)(struct rtw_hal_com_t *hal, u32 addr);
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#ifdef DBG_PHL_MAC_REG_RW
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if (rtw_hal_mac_reg_chk(hal, addr) == false) {
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r_val = 0xEAEA;
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return r_val;
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}
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#endif
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_read16 = io_priv->io_ops._read16;
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r_val = _read16(hal, addr);
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return r_val;
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}
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u32 _hal_read32(struct rtw_hal_com_t *hal, u32 addr)
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{
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u32 r_val;
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struct hal_io_priv *io_priv = &hal->iopriv;
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u32(*_read32)(struct rtw_hal_com_t *hal, u32 addr);
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#ifdef DBG_PHL_MAC_REG_RW
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if (rtw_hal_mac_reg_chk(hal, addr) == false) {
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r_val = 0xEAEAEAEA;
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return r_val;
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}
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#endif
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_read32 = io_priv->io_ops._read32;
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r_val = _read32(hal, addr);
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return r_val;
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}
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int _hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val)
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{
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struct hal_io_priv *io_priv = &hal->iopriv;
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int (*_write8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
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#ifdef RTW_WKARD_BUS_WRITE
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int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr,
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u32 value) = NULL;
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#endif
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int ret;
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#ifdef DBG_PHL_MAC_REG_RW
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if (rtw_hal_mac_reg_chk(hal, addr) == false)
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return 0;
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#endif
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_write8 = io_priv->io_ops._write8;
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ret = _write8(hal, addr, val);
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#ifdef RTW_WKARD_BUS_WRITE
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_write_post_cfg = io_priv->io_ops._write_post_cfg;
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if(NULL != _write_post_cfg) {
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ret = _write_post_cfg(hal, addr, val);
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}
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#endif
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return ret;
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}
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int _hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val)
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{
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struct hal_io_priv *io_priv = &hal->iopriv;
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int (*_write16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
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#ifdef RTW_WKARD_BUS_WRITE
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int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr,
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u32 value) = NULL;
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#endif
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int ret;
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#ifdef DBG_PHL_MAC_REG_RW
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if (rtw_hal_mac_reg_chk(hal, addr) == false)
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return 0;
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#endif
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_write16 = io_priv->io_ops._write16;
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ret = _write16(hal, addr, val);
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#ifdef RTW_WKARD_BUS_WRITE
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_write_post_cfg = io_priv->io_ops._write_post_cfg;
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if(NULL != _write_post_cfg) {
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ret = _write_post_cfg(hal, addr, val);
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}
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#endif
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return ret;
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}
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int _hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val)
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{
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struct hal_io_priv *io_priv = &hal->iopriv;
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int (*_write32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
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#ifdef RTW_WKARD_BUS_WRITE
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int (*_write_post_cfg)(struct rtw_hal_com_t *hal, u32 addr,
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u32 value) = NULL;
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#endif
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int ret;
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#ifdef DBG_PHL_MAC_REG_RW
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if (rtw_hal_mac_reg_chk(hal, addr) == false)
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return 0;
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#endif
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_write32 = io_priv->io_ops._write32;
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ret = _write32(hal, addr, val);
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#ifdef RTW_WKARD_BUS_WRITE
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_write_post_cfg = io_priv->io_ops._write_post_cfg;
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if(NULL != _write_post_cfg) {
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ret = _write_post_cfg(hal, addr, val);
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}
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#endif
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return ret;
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}
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#ifdef CONFIG_SDIO_HCI
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u8 _hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr)
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{
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u8 r_val = 0x00;
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struct hal_io_priv *io_priv = &hal->iopriv;
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u8(*_sd_f0_read8)(struct rtw_hal_com_t *hal, u32 addr);
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_sd_f0_read8 = io_priv->io_ops._sd_f0_read8;
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if (_sd_f0_read8)
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r_val = _sd_f0_read8(hal, addr);
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return r_val;
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}
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#ifdef CONFIG_SDIO_INDIRECT_ACCESS
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u8 _hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr)
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{
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u8 r_val = 0x00;
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struct hal_io_priv *io_priv = &hal->iopriv;
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u8(*_sd_iread8)(struct rtw_hal_com_t *hal, u32 addr);
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_sd_iread8 = io_priv->io_ops._sd_iread8;
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if (_sd_iread8)
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r_val = _sd_iread8(hal, addr);
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return r_val;
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}
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u16 _hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr)
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{
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u16 r_val = 0x00;
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struct hal_io_priv *io_priv = &hal->iopriv;
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u16(*_sd_iread16)(struct rtw_hal_com_t *hal, u32 addr);
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_sd_iread16 = io_priv->io_ops._sd_iread16;
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if (_sd_iread16)
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r_val = _sd_iread16(hal, addr);
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return r_val;
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}
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u32 _hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr)
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{
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u32 r_val = 0x00;
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struct hal_io_priv *io_priv = &hal->iopriv;
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u32(*_sd_iread32)(struct rtw_hal_com_t *hal, u32 addr);
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_sd_iread32 = io_priv->io_ops._sd_iread32;
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if (_sd_iread32)
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r_val = _sd_iread32(hal, addr);
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return r_val;
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}
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int _hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val)
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{
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struct hal_io_priv *io_priv = &hal->iopriv;
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int (*_sd_iwrite8)(struct rtw_hal_com_t *hal, u32 addr, u8 val);
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int ret = -1;
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_sd_iwrite8 = io_priv->io_ops._sd_iwrite8;
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if (_sd_iwrite8)
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ret = _sd_iwrite8(hal, addr, val);
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return ret;
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}
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int _hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val)
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{
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struct hal_io_priv *io_priv = &hal->iopriv;
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int (*_sd_iwrite16)(struct rtw_hal_com_t *hal, u32 addr, u16 val);
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int ret = -1;
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_sd_iwrite16 = io_priv->io_ops._sd_iwrite16;
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if (_sd_iwrite16)
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ret = _sd_iwrite16(hal, addr, val);
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return ret;
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}
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int _hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val)
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{
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struct hal_io_priv *io_priv = &hal->iopriv;
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int (*_sd_iwrite32)(struct rtw_hal_com_t *hal, u32 addr, u32 val);
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int ret = -1;
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_sd_iwrite32 = io_priv->io_ops._sd_iwrite32;
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if (_sd_iwrite32)
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ret = _sd_iwrite32(hal, addr, val);
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return ret;
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}
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#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
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#endif /* CONFIG_SDIO_HCI */
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u32 hal_init_io_priv(struct rtw_hal_com_t *hal,
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void (*set_intf_ops)(struct rtw_hal_com_t *hal, struct hal_io_ops *ops))
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{
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struct hal_io_priv *iopriv = &hal->iopriv;
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if (set_intf_ops == NULL)
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return RTW_HAL_STATUS_IO_INIT_FAILURE;
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#ifdef CONFIG_SDIO_INDIRECT_ACCESS
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_os_mutex_init(hal->drv_priv, &iopriv->sd_indirect_access_mutex);
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#endif
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set_intf_ops(hal, &iopriv->io_ops);
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return RTW_HAL_STATUS_SUCCESS;
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}
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u32 hal_deinit_io_priv(struct rtw_hal_com_t *hal)
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{
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#ifdef CONFIG_SDIO_INDIRECT_ACCESS
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struct hal_io_priv *iopriv = &hal->iopriv;
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_os_mutex_init(hal->drv_priv, &iopriv->sd_indirect_access_mutex);
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#endif
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return RTW_HAL_STATUS_SUCCESS;
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}
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/*******************common IO APIs *******************/
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static inline u32 _bit_shift(u32 mask)
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{
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u32 i;
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for (i = 0; i <= 31; i++)
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if (mask & BIT(i))
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break;
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return i;
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}
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u32 hal_read_macreg(struct hal_info_t *hal,
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u32 offset, u32 bit_mask)
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{
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u32 val = 0, val32, shift;
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val32 = hal_read32(hal->hal_com, offset);
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if (bit_mask != 0xFFFFFFFF) {
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shift = _bit_shift(bit_mask);
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val = (val32 & bit_mask) >> shift;
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return val;
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}
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else {
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return val32;
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}
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}
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void hal_write_macreg(struct hal_info_t *hal,
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u32 offset, u32 bit_mask, u32 data)
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{
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u32 val32, shift;
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if (bit_mask != 0xFFFFFFFF) {
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val32 = hal_read32(hal->hal_com, offset);
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shift = _bit_shift(bit_mask);
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data = ((val32 & (~bit_mask)) | ((data << shift) & bit_mask));
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}
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hal_write32(hal->hal_com, offset, data);
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}
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u32 hal_read_bbreg(struct hal_info_t *hal,
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u32 offset, u32 bit_mask)
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{
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u32 val32 = 0;
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val32 = rtw_hal_read_bb_reg(hal->hal_com, offset, bit_mask);
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return val32;
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}
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void hal_write_bbreg(struct hal_info_t *hal,
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u32 offset, u32 bit_mask, u32 data)
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{
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rtw_hal_write_bb_reg(hal->hal_com, offset, bit_mask, data);
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}
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u32 hal_read_rfreg(struct hal_info_t *hal,
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enum rf_path path, u32 offset, u32 bit_mask)
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{
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u32 val32 = 0;
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val32 = rtw_hal_read_rf_reg(hal->hal_com, path, offset, bit_mask);
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#ifdef DBG_IO
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if (match_rf_read_sniff_ranges(hal->hal_com, path, offset, bit_mask)) {
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PHL_INFO("DBG_IO hal_read_rfreg(%u, 0x%04x, 0x%08x) read:0x%08x(0x%08x)\n"
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, path, offset, bit_mask, (val32 << _bit_shift(bit_mask)), val32);
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}
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#endif
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return val32;
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}
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void hal_write_rfreg(struct hal_info_t *hal,
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enum rf_path path, u32 offset, u32 bit_mask, u32 data)
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{
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rtw_hal_write_rf_reg(hal->hal_com, path, offset, bit_mask, data);
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#ifdef DBG_IO
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if (match_rf_write_sniff_ranges(hal->hal_com, path, offset, bit_mask)) {
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PHL_INFO("DBG_IO hal_write_rfreg(%u, 0x%04x, 0x%08x) write:0x%08x(0x%08x)\n"
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, path, offset, bit_mask, (data << _bit_shift(bit_mask)), data);
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}
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#endif
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}
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static u32 _cal_bit_shift(u32 bit_mask)
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{
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u32 i;
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for (i = 0; i <= 31; i++) {
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if (((bit_mask >> i) & 0x1) == 1)
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break;
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}
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return (i);
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}
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void hal_write32_mask(struct rtw_hal_com_t *hal, u16 addr, u32 mask, u32 val)
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{
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u32 original_value, new_value;
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u32 bit_shift;
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if (mask == 0xFFFFFFFF) {
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hal_write32(hal, addr, val);
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} else {
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original_value = hal_read32(hal, addr);
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bit_shift = _cal_bit_shift(mask);
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new_value = (((original_value) & (~mask)) | ((val << bit_shift) & mask));
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hal_write32(hal, addr, new_value);
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}
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}
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#ifdef DBG_IO
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#define RTW_IO_SNIFF_TYPE_RANGE 0 /* specific address range is accessed */
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#define RTW_IO_SNIFF_TYPE_VALUE 1 /* value match for sniffed range */
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struct rtw_io_sniff_ent {
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u8 chip;
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u8 hci;
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u32 addr;
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u8 type;
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union {
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u32 end_addr;
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struct {
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u32 mask;
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u32 val;
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bool equal;
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} vm; /* value match */
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} u;
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bool trace;
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char *tag;
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};
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#define RTW_IO_SNIFF_RANGE_ENT(_chip, _hci, _addr, _end_addr, _trace, _tag) \
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{.chip = _chip, .hci = _hci, .addr = _addr, .u.end_addr = _end_addr, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_RANGE,}
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#define RTW_IO_SNIFF_VALUE_ENT(_chip, _hci, _addr, _mask, _val, _equal, _trace, _tag) \
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{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = _val, .u.vm.equal = _equal, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
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/* part or all sniffed range is enabled (not all 0) */
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#define RTW_IO_SNIFF_EN_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
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{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
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/* part or all sniffed range is disabled (not all 1) */
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#define RTW_IO_SNIFF_DIS_ENT(_chip, _hci, _addr, _mask, _trace, _tag) \
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{.chip = _chip, .hci = _hci, .addr = _addr, .u.vm.mask = _mask, .u.vm.val = 0xFFFFFFFF, .u.vm.equal = 0, .trace = _trace, .tag = _tag, .type = RTW_IO_SNIFF_TYPE_VALUE,}
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const struct rtw_io_sniff_ent read_sniff[] = {
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#ifdef DBG_IO_HCI_EN_CHK
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RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
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RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_USB, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
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RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_PCIE, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
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#endif
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#ifdef DBG_IO_SNIFF_EXAMPLE
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RTW_IO_SNIFF_RANGE_ENT(CHIP_WIFI6_MAX, 0, 0x522, 0x522, 0, "read TXPAUSE"),
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RTW_IO_SNIFF_DIS_ENT(CHIP_WIFI6_MAX, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
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#endif
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};
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const int read_sniff_num = sizeof(read_sniff) / sizeof(struct rtw_io_sniff_ent);
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const struct rtw_io_sniff_ent write_sniff[] = {
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#ifdef DBG_IO_HCI_EN_CHK
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RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1FC, 1, "SDIO 0x02[8:2] not all 0"),
|
|
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x1E0, 1, "USB 0x02[8:5] not all 0"),
|
|
RTW_IO_SNIFF_EN_ENT(CHIP_WIFI6_MAX, RTW_HCI_SDIO, 0x02, 0x01C, 1, "PCI 0x02[4:2] not all 0"),
|
|
#endif
|
|
#ifdef DBG_IO_SNIFF_EXAMPLE
|
|
RTW_IO_SNIFF_RANGE_ENT(CHIP_WIFI6_MAX, 0, 0x522, 0x522, 0, "write TXPAUSE"),
|
|
RTW_IO_SNIFF_DIS_ENT(CHIP_WIFI6_MAX, 0, 0x02, 0x3, 0, "0x02[1:0] not all 1"),
|
|
#endif
|
|
};
|
|
|
|
const int write_sniff_num = sizeof(write_sniff) / sizeof(struct rtw_io_sniff_ent);
|
|
|
|
static bool match_io_sniff_ranges(struct rtw_hal_com_t *hal
|
|
, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u16 len)
|
|
{
|
|
|
|
/* check if IO range after sniff end address */
|
|
if (addr > sniff->u.end_addr)
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static bool match_io_sniff_value(struct rtw_hal_com_t *hal
|
|
, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
|
|
{
|
|
u8 sniff_len;
|
|
s8 mask_shift;
|
|
u32 mask;
|
|
s8 value_shift;
|
|
u32 value;
|
|
bool ret = 0;
|
|
|
|
/* check if IO range after sniff end address */
|
|
sniff_len = 4;
|
|
while (!(sniff->u.vm.mask & (0xFF << ((sniff_len - 1) * 8)))) {
|
|
sniff_len--;
|
|
if (sniff_len == 0)
|
|
goto exit;
|
|
}
|
|
if (sniff->addr + sniff_len <= addr)
|
|
goto exit;
|
|
|
|
/* align to IO addr */
|
|
mask_shift = (sniff->addr - addr) * 8;
|
|
value_shift = mask_shift + bitshift(sniff->u.vm.mask);
|
|
if (mask_shift > 0)
|
|
mask = sniff->u.vm.mask << mask_shift;
|
|
else if (mask_shift < 0)
|
|
mask = sniff->u.vm.mask >> -mask_shift;
|
|
else
|
|
mask = sniff->u.vm.mask;
|
|
|
|
if (value_shift > 0)
|
|
value = sniff->u.vm.val << value_shift;
|
|
else if (mask_shift < 0)
|
|
value = sniff->u.vm.val >> -value_shift;
|
|
else
|
|
value = sniff->u.vm.val;
|
|
|
|
if ((sniff->u.vm.equal && (mask & val) == (mask & value))
|
|
|| (!sniff->u.vm.equal && (mask & val) != (mask & value))
|
|
) {
|
|
ret = 1;
|
|
if (0)
|
|
PHL_INFO(" addr:0x%x len:%u val:0x%x (i:%d sniff_len:%u m_shift:%d mask:0x%x v_shifd:%d value:0x%x equal:%d)\n"
|
|
, addr, len, val, i, sniff_len, mask_shift, mask, value_shift, value, sniff->u.vm.equal);
|
|
}
|
|
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
static bool match_io_sniff(struct rtw_hal_com_t *hal
|
|
, const struct rtw_io_sniff_ent *sniff, int i, u32 addr, u8 len, u32 val)
|
|
{
|
|
bool ret = 0;
|
|
|
|
if (sniff->chip != CHIP_WIFI6_MAX
|
|
&& sniff->chip != hal_get_chip_id(hal))
|
|
goto exit;
|
|
/*
|
|
if (sniff->hci
|
|
&& !(sniff->hci & hal_get_hci_type(hal)))
|
|
goto exit;
|
|
*/
|
|
if (sniff->addr >= addr + len) /* IO range below sniff start address */
|
|
goto exit;
|
|
|
|
switch (sniff->type) {
|
|
case RTW_IO_SNIFF_TYPE_RANGE:
|
|
ret = match_io_sniff_ranges(hal, sniff, i, addr, len);
|
|
break;
|
|
case RTW_IO_SNIFF_TYPE_VALUE:
|
|
if (len == 1 || len == 2 || len == 4)
|
|
ret = match_io_sniff_value(hal, sniff, i, addr, len, val);
|
|
break;
|
|
default:
|
|
/*_os_warn_on(1);*/
|
|
break;
|
|
}
|
|
|
|
exit:
|
|
return ret;
|
|
}
|
|
|
|
u32 match_read_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val)
|
|
{
|
|
int i;
|
|
bool trace = 0;
|
|
u32 match = 0;
|
|
|
|
for (i = 0; i < read_sniff_num; i++) {
|
|
if (match_io_sniff(hal, &read_sniff[i], i, addr, len, val)) {
|
|
match++;
|
|
trace |= read_sniff[i].trace;
|
|
if (read_sniff[i].tag)
|
|
PHL_INFO("DBG_IO TAG %s\n", read_sniff[i].tag);
|
|
}
|
|
}
|
|
|
|
/*_os_warn_on(trace);*/
|
|
|
|
return match;
|
|
}
|
|
|
|
u32 match_write_sniff(struct rtw_hal_com_t *hal, u32 addr, u16 len, u32 val)
|
|
{
|
|
int i;
|
|
bool trace = 0;
|
|
u32 match = 0;
|
|
|
|
for (i = 0; i < write_sniff_num; i++) {
|
|
if (match_io_sniff(hal, &write_sniff[i], i, addr, len, val)) {
|
|
match++;
|
|
trace |= write_sniff[i].trace;
|
|
if (write_sniff[i].tag)
|
|
PHL_INFO("DBG_IO TAG %s\n", write_sniff[i].tag);
|
|
}
|
|
}
|
|
|
|
/*_os_warn_on(trace);*/
|
|
|
|
return match;
|
|
}
|
|
|
|
struct rf_sniff_ent {
|
|
u8 path;
|
|
u16 reg;
|
|
u32 mask;
|
|
};
|
|
|
|
struct rf_sniff_ent rf_read_sniff_ranges[] = {
|
|
/* example for all path addr 0x55 with all RF Reg mask */
|
|
/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
|
|
};
|
|
|
|
struct rf_sniff_ent rf_write_sniff_ranges[] = {
|
|
/* example for all path addr 0x55 with all RF Reg mask */
|
|
/* {MAX_RF_PATH, 0x55, bRFRegOffsetMask}, */
|
|
};
|
|
|
|
int rf_read_sniff_num = sizeof(rf_read_sniff_ranges) / sizeof(struct rf_sniff_ent);
|
|
int rf_write_sniff_num = sizeof(rf_write_sniff_ranges) / sizeof(struct rf_sniff_ent);
|
|
|
|
bool match_rf_read_sniff_ranges(struct rtw_hal_com_t *hal, u8 path, u32 addr, u32 mask)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < rf_read_sniff_num; i++) {
|
|
if (rf_read_sniff_ranges[i].path == MAX_RF_PATH ||
|
|
rf_read_sniff_ranges[i].path == path)
|
|
if ((addr == rf_read_sniff_ranges[i].reg) &&
|
|
(mask & rf_read_sniff_ranges[i].mask))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool match_rf_write_sniff_ranges(struct rtw_hal_com_t *hal,
|
|
u8 path, u32 addr, u32 mask)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < rf_write_sniff_num; i++) {
|
|
if (rf_write_sniff_ranges[i].path == MAX_RF_PATH ||
|
|
rf_write_sniff_ranges[i].path == path)
|
|
if ((addr == rf_write_sniff_ranges[i].reg) &&
|
|
(mask & rf_write_sniff_ranges[i].mask))
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
u8 dbg_hal_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
|
|
{
|
|
u8 val = _hal_read8(hal, addr);
|
|
|
|
if (match_read_sniff(hal, addr, 1, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_read8(0x%04x) return 0x%02x\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
u16 dbg_hal_read16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
|
|
{
|
|
u16 val = _hal_read16(hal, addr);
|
|
|
|
if (match_read_sniff(hal, addr, 2, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_read16(0x%04x) return 0x%04x\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
u32 dbg_hal_read32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
|
|
{
|
|
u32 val = _hal_read32(hal, addr);
|
|
|
|
if (match_read_sniff(hal, addr, 4, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_read32(0x%04x) return 0x%08x\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
int dbg_hal_write8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line)
|
|
{
|
|
if (match_write_sniff(hal, addr, 1, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_write8(0x%04x, 0x%02x)\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return _hal_write8(hal, addr, val);
|
|
}
|
|
int dbg_hal_write16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line)
|
|
{
|
|
if (match_write_sniff(hal, addr, 2, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_write16(0x%04x, 0x%04x)\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return _hal_write16(hal, addr, val);
|
|
}
|
|
int dbg_hal_write32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line)
|
|
{
|
|
if (match_write_sniff(hal, addr, 4, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_write32(0x%04x, 0x%08x)\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return _hal_write32(hal, addr, val);
|
|
}
|
|
|
|
#ifdef CONFIG_SDIO_HCI
|
|
u8 dbg_hal_sd_f0_read8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
|
|
{
|
|
u8 val = _hal_sd_f0_read8(hal, addr);
|
|
|
|
#if 0
|
|
if (match_read_sniff(adapter, addr, 1, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_sd_f0_read8(0x%04x) return 0x%02x\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
#endif
|
|
|
|
return val;
|
|
}
|
|
|
|
#ifdef CONFIG_SDIO_INDIRECT_ACCESS
|
|
u8 dbg_hal_sd_iread8(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
|
|
{
|
|
u8 val = hal_sd_iread8(hal, addr);
|
|
|
|
if (match_read_sniff(hal, addr, 1, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_sd_iread8(0x%04x) return 0x%02x\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
u16 dbg_hal_sd_iread16(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
|
|
{
|
|
u16 val = _hal_sd_iread16(hal, addr);
|
|
|
|
if (match_read_sniff(hal, addr, 2, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_sd_iread16(0x%04x) return 0x%04x\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
u32 dbg_hal_sd_iread32(struct rtw_hal_com_t *hal, u32 addr, const char *caller, const int line)
|
|
{
|
|
u32 val = _hal_sd_iread32(hal, addr);
|
|
|
|
if (match_read_sniff(hal, addr, 4, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_sd_iread32(0x%04x) return 0x%08x\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return val;
|
|
}
|
|
|
|
int dbg_hal_sd_iwrite8(struct rtw_hal_com_t *hal, u32 addr, u8 val, const char *caller, const int line)
|
|
{
|
|
if (match_write_sniff(hal, addr, 1, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_sd_iwrite8(0x%04x, 0x%02x)\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return _hal_sd_iwrite8(hal, addr, val);
|
|
}
|
|
int dbg_hal_sd_iwrite16(struct rtw_hal_com_t *hal, u32 addr, u16 val, const char *caller, const int line)
|
|
{
|
|
if (match_write_sniff(hal, addr, 2, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_sd_iwrite16(0x%04x, 0x%04x)\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return _hal_sd_iwrite16(hal, addr, val);
|
|
}
|
|
int dbg_hal_sd_iwrite32(struct rtw_hal_com_t *hal, u32 addr, u32 val, const char *caller, const int line)
|
|
{
|
|
if (match_write_sniff(hal, addr, 4, val)) {
|
|
PHL_INFO("DBG_IO %s:%d hal_sd_iwrite32(0x%04x, 0x%08x)\n"
|
|
, caller, line, addr, val);
|
|
}
|
|
|
|
return _hal_sd_iwrite32(hal, addr, val);
|
|
}
|
|
|
|
#endif /* CONFIG_SDIO_INDIRECT_ACCESS */
|
|
|
|
#endif /* CONFIG_SDIO_HCI */
|
|
#endif
|