/*
 * (C) Copyright 2020 Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

/ {
	aliases {
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		mmc0 = &sdhci;
		mmc1 = &sdmmc0;
		mmc2 = &sdmmc1;
	};

	chosen {
		stdout-path = &uart2;
		u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
	};

	secure-otp@fe3a0000 {
		compatible = "rockchip,rk3568-secure-otp";
		reg = <0x0 0xfe3a0000 0x0 0x4000>;
		secure_conf = <0xfdd18008>;
		mask_addr = <0xfe880000>;
		cru_rst_addr = <0xfdd20470>;
		u-boot,dm-spl;
	};
};

&i2c0 {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
        status = "okay";
};
&i2c0_xfer {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
        status = "okay";
};
&pcfg_pull_none_smt {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
        status = "okay";
};

&psci {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&crypto {
	u-boot,dm-spl;
};

&uart2 {
	clock-frequency = <24000000>;
	u-boot,dm-spl;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	status = "okay";
};

&grf {
	u-boot,dm-spl;
	status = "okay";
};

&pmugrf {
	u-boot,dm-spl;
	status = "okay";
};

&usb2phy0_grf {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbdrd30 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbdrd_dwc3 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbhost30 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usbhost_dwc3 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usb2phy0 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&u2phy0_otg {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&u2phy0_host {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&cru {
	u-boot,dm-spl;
	status = "okay";
};

&pmucru {
	u-boot,dm-spl;
	status = "okay";
};

&pmugrf {
	u-boot,dm-spl;
	status = "okay";
};

&rng {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&sfc {
	u-boot,dm-spl;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	spi_nand: flash@0 {
		u-boot,dm-spl;
		compatible = "spi-nand";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <75000000>;
	};

	spi_nor: flash@1 {
		u-boot,dm-spl;
		compatible = "jedec,spi-nor";
		label = "sfc_nor";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <100000000>;
	};
};

&saradc {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&sdmmc0 {
	u-boot,dm-spl;
	status = "okay";
};

&sdmmc0_pins {
	u-boot,dm-spl;
};

&sdmmc0_bus4 {
	u-boot,dm-spl;
};

&sdmmc0_clk {
	u-boot,dm-spl;
};

&sdmmc0_cmd {
	u-boot,dm-spl;
};

&sdmmc0_det {
	u-boot,dm-spl;
};

&sdmmc1 {
	u-boot,dm-spl;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	status = "okay";
};

&sdhci {
	bus-width = <8>;
	u-boot,dm-spl;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	mmc-hs200-1_8v;
	status = "okay";
};

&nandc0 {
	u-boot,dm-spl;
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;

	nand@0 {
		u-boot,dm-spl;
		reg = <0>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <16>;
		nand-ecc-step-size = <1024>;
	};
};

&gmac0_clkin {
	u-boot,dm-pre-reloc;
};

&gmac1_clkin {
	u-boot,dm-pre-reloc;
};

&gmac0 {
	u-boot,dm-pre-reloc;
	phy-mode = "rgmii";
	clock_in_out = "output";

	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 20ms, 100ms for rtl8211f */
	snps,reset-delays-us = <0 20000 100000>;
	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&gmac0_miim
		     &gmac0_tx_bus2
		     &gmac0_rx_bus2
		     &gmac0_rgmii_clk
		     &gmac0_rgmii_bus>;

	tx_delay = <0x3c>;
	rx_delay = <0x2f>;

	phy-handle = <&rgmii_phy0>;
	status = "disabled";
};

&gmac1 {
	u-boot,dm-pre-reloc;
	phy-mode = "rgmii";
	clock_in_out = "output";

	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
	snps,reset-active-low;
	/* Reset time is 20ms, 100ms for rtl8211f */
	snps,reset-delays-us = <0 20000 100000>;

	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
	assigned-clock-rates = <0>, <125000000>;

	pinctrl-names = "default";
	pinctrl-0 = <&gmac1m1_miim
		     &gmac1m1_tx_bus2
		     &gmac1m1_rx_bus2
		     &gmac1m1_rgmii_clk
		     &gmac1m1_rgmii_bus>;

	tx_delay = <0x4f>;
	rx_delay = <0x26>;

	phy-handle = <&rgmii_phy1>;
	status = "disabled";
};

&gmac0_stmmac_axi_setup {
	u-boot,dm-pre-reloc;
};

&gmac0_mtl_rx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&gmac0_mtl_tx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&gmac1_stmmac_axi_setup {
	u-boot,dm-pre-reloc;
};

&gmac1_mtl_rx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&gmac1_mtl_tx_setup {
	u-boot,dm-pre-reloc;
	queue0 {
		u-boot,dm-pre-reloc;
	};
};

&mdio0 {
	u-boot,dm-pre-reloc;
	rgmii_phy0: phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		u-boot,dm-pre-reloc;
		reg = <0x0>;
	};
};

&mdio1 {
	u-boot,dm-pre-reloc;
	rgmii_phy1: phy@0 {
		compatible = "ethernet-phy-ieee802.3-c22";
		u-boot,dm-pre-reloc;
		reg = <0x0>;
	};
};

&gmac0_miim {
	u-boot,dm-pre-reloc;
};

&gmac0_clkinout {
	u-boot,dm-pre-reloc;
};

&gmac0_rx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac0_tx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac0_rgmii_clk {
	u-boot,dm-pre-reloc;
};

&gmac0_rgmii_bus {
	u-boot,dm-pre-reloc;
};

&gmac1m1_miim {
	u-boot,dm-pre-reloc;
};

&gmac1m1_clkinout {
	u-boot,dm-pre-reloc;
};

&gmac1m1_rx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac1m1_tx_bus2 {
	u-boot,dm-pre-reloc;
};

&gmac1m1_rgmii_clk {
	u-boot,dm-pre-reloc;
};

&gmac1m1_rgmii_bus {
	u-boot,dm-pre-reloc;
};

&eth0_clkout_pins {
	u-boot,dm-pre-reloc;
};

&eth1m1_clkout_pins {
	u-boot,dm-pre-reloc;
};

&pcie30phy {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&pcie3x2 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&pinctrl {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&gpio0 {
	u-boot,dm-spl;
};

&gpio1 {
	u-boot,dm-spl;
};

&gpio2 {
	u-boot,dm-spl;
};

&pcfg_pull_none_drv_level_1 {
	u-boot,dm-spl;
};

&pcfg_pull_none_drv_level_2 {
	u-boot,dm-spl;
};


&pcfg_pull_up_drv_level_1 {
	u-boot,dm-spl;
};

&pcfg_pull_up_drv_level_2 {
	u-boot,dm-spl;
};

&pcfg_pull_up {
	u-boot,dm-spl;
};

&pcfg_pull_none {
	u-boot,dm-spl;
};

&wdt {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&otp {
	u-boot,dm-spl;
	status = "okay";
};

#if 0
&i2c0 {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
	status = "okay";
	i2c_eeprom:eeprom@51 {
		compatible = "atmel,24c256", "i2c-eeprom";
                reg = <0x51>;
                pagesize = <64>;
	};
};
&i2c0_xfer {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
	status = "okay";
};
&pcfg_pull_none_smt {
	u-boot,dm-spl;
	u-boot,dm-pre-reloc;
        status = "okay";
};

&i2c1 {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&i2c1_xfer {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&pcfg_pull_none_smt {
	u-boot,dm-pre-reloc;
	status = "okay";
};
#endif