74 lines
1.7 KiB
Plaintext
74 lines
1.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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# common clock support for ROCKCHIP SoC family.
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config COMMON_CLK_ROCKCHIP
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tristate "Rockchip clock controller common support"
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depends on ARCH_ROCKCHIP
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default ARCH_ROCKCHIP
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help
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Say y here to enable common clock controller for Rockchip platforms.
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if COMMON_CLK_ROCKCHIP
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config ROCKCHIP_CLK_COMPENSATION
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bool "Rockchip Clk Compensation"
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help
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Say y here to enable clk compensation(+/- 1000 ppm).
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config ROCKCHIP_CLK_BOOST
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bool "Rockchip Clk Boost"
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default y if CPU_PX30
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help
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Say y here to enable clk boost.
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config ROCKCHIP_CLK_INV
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bool "Rockchip Clk Inverter"
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default y if !CPU_RV1126
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help
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Say y here to enable clk Inverter.
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config ROCKCHIP_CLK_OUT
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tristate "Rockchip Clk Out / Input Switch"
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default y if !CPU_RV1126
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help
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Say y here to enable clk out / input switch.
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config ROCKCHIP_CLK_PVTM
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bool "Rockchip Clk Pvtm"
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default y if !CPU_RV1126
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help
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Say y here to enable clk pvtm.
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config ROCKCHIP_DCLK_DIV
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bool "Rockchip Dclk Divider"
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default y if !CPU_RV1126
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help
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Say y here to enable dclk divider.
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config ROCKCHIP_DDRCLK_SCPI
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bool "Rockchip DDR Clk SCPI"
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default y if RK3368_SCPI_PROTOCOL
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help
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Say y here to enable ddr clk scpi.
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config ROCKCHIP_DDRCLK_SIP
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bool "Rockchip DDR Clk SIP"
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default y if CPU_RK3399
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help
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Say y here to enable ddr clk sip.
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config ROCKCHIP_PLL_RK3066
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bool "Rockchip PLL Type RK3066"
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default y if CPU_RK30XX || CPU_RK3188 || \
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CPU_RK3288 || CPU_RK3368
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help
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Say y here to enable pll type is rk3066.
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config ROCKCHIP_PLL_RK3399
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bool "Rockchip PLL Type RK3399"
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default y if CPU_RK3399 || CPU_RV110X
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help
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Say y here to enable pll type is rk3399.
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endif
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source "drivers/clk/rockchip/regmap/Kconfig"
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