121 lines
2.9 KiB
Plaintext
121 lines
2.9 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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#include "rk3568.dtsi"
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&cru {
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/* remove PLL_NPLL and ACLK_VOP */
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assigned-clocks =
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<&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>,
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<&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>,
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<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
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<&cru CPLL_500M>, <&cru CPLL_333M>,
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<&cru CPLL_250M>, <&cru CPLL_125M>,
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<&cru CPLL_100M>, <&cru CPLL_62P5M>,
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<&cru CPLL_50M>, <&cru CPLL_25M>,
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<&cru PLL_GPLL>,
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<&cru ACLK_BUS>, <&cru PCLK_BUS>,
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<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
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<&cru HCLK_TOP>, <&cru PCLK_TOP>,
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<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
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<&cru ACLK_PIPE>,
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<&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>,
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<&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>,
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<&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>,
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<&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>,
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<&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>;
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assigned-clock-rates =
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<32768>, <300000000>,
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<300000000>, <200000000>,
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<100000000>, <1000000000>,
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<500000000>, <333000000>,
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<250000000>, <125000000>,
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<100000000>, <62500000>,
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<50000000>, <25000000>,
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<1188000000>,
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<150000000>, <100000000>,
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<500000000>, <400000000>,
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<150000000>, <100000000>,
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<300000000>, <150000000>,
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<400000000>,
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<100000000>, <1188000000>,
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<1188000000>, <1188000000>,
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<1188000000>, <1188000000>,
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<1188000000>, <1188000000>,
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<1188000000>, <1188000000>;
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assigned-clock-parents =
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<&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>,
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<&cru PLL_GPLL>;
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};
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&cpu0_opp_table {
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/delete-node/ mbist-vmin;
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/delete-node/ opp-408000000;
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/delete-node/ opp-600000000;
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/delete-node/ opp-816000000;
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/delete-node/ opp-1104000000;
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/delete-node/ opp-1416000000;
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/delete-node/ opp-1608000000;
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/delete-node/ opp-1800000000;
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/delete-node/ opp-1992000000;
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opp-1416000000 {
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opp-hz = /bits/ 64 <1416000000>;
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opp-microvolt = <900000 900000 900000>;
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clock-latency-ns = <40000>;
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};
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};
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&display_subsystem {
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status = "disabled";
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};
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&dmc {
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system-status-level = <
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/*system status freq level*/
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SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH
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>;
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auto-freq-en = <0>;
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};
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&dmc_opp_table {
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/delete-node/ mbist-vmin;
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/delete-node/ opp-1560000000;
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opp-780000000 {
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opp-hz = /bits/ 64 <780000000>;
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opp-microvolt = <875000>;
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};
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};
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&gpu_opp_table {
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/delete-node/ mbist-vmin;
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/delete-node/ opp-200000000;
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/delete-node/ opp-300000000;
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/delete-node/ opp-400000000;
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/delete-node/ opp-600000000;
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/delete-node/ opp-700000000;
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/delete-node/ opp-800000000;
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <900000>;
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};
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};
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&npu_opp_table {
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/delete-node/ mbist-vmin;
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/delete-node/ opp-200000000;
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/delete-node/ opp-300000000;
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/delete-node/ opp-400000000;
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/delete-node/ opp-600000000;
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/delete-node/ opp-700000000;
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/delete-node/ opp-800000000;
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/delete-node/ opp-900000000;
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <900000 900000 900000>;
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};
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};
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