308 lines
7.9 KiB
Plaintext
308 lines
7.9 KiB
Plaintext
/*
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* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/display/drm_mipi_dsi.h>
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#include "rk3399-vop-clk-set.dtsi"
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/ {
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compatible = "rockchip,linux", "rockchip,rk3399";
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aliases {
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mmc0 = &sdhci;
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mmc1 = &sdmmc;
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mmc2 = &sdio0;
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};
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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drm_logo: drm-logo@00000000 {
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compatible = "rockchip,drm-logo";
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reg = <0x0 0x0 0x0 0x0>;
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};
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ramoops: ramoops@110000 {
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compatible = "ramoops";
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reg = <0x0 0x110000 0x0 0xf0000>;
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record-size = <0x20000>;
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console-size = <0x80000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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};
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fiq_debugger: fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,signal-irq = <182>;
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rockchip,wake-irq = <0>;
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rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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pinctrl-names = "default";
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pinctrl-0 = <&uart2c_xfer>;
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};
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cif_isp0: cif_isp@ff910000 {
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compatible = "rockchip,rk3399-cif-isp";
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rockchip,grf = <&grf>;
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reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
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reg-names = "register", "dsihost-register";
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clocks =
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<&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
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<&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
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<&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>,
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<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
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<&cru SCLK_MIPIDPHY_REF>;
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clock-names =
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"aclk_isp0_noc", "aclk_isp0_wrapper",
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"hclk_isp0_noc", "hclk_isp0_wrapper",
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"clk_isp0", "pclk_dphyrx",
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"clk_cif_out", "clk_cif_pll",
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"pclk_dphy_ref";
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "cif_isp10_irq";
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power-domains = <&power RK3399_PD_ISP0>;
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rockchip,isp,iommu-enable = <1>;
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iommus = <&isp0_mmu>;
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status = "disabled";
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};
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cif_isp1: cif_isp@ff920000 {
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compatible = "rockchip,rk3399-cif-isp";
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rockchip,grf = <&grf>;
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reg = <0x0 0xff920000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
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reg-names = "register", "dsihost-register";
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clocks =
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<&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
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<&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
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<&cru SCLK_ISP1>, <&cru PCLK_ISP1_WRAPPER>,
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<&cru SCLK_DPHY_TX1RX1_CFG>,
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<&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>,
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<&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
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<&cru SCLK_MIPIDPHY_REF>;
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clock-names =
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"aclk_isp1_noc", "aclk_isp1_wrapper",
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"hclk_isp1_noc", "hclk_isp1_wrapper",
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"clk_isp1", "pclkin_isp1",
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"pclk_dphytxrx",
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"pclk_mipi_dsi","mipi_dphy_cfg",
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"clk_cif_out", "clk_cif_pll",
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"pclk_dphy_ref";
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
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interrupt-names = "cif_isp10_irq";
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power-domains = <&power RK3399_PD_ISP1>;
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rockchip,isp,iommu-enable = <1>;
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iommus = <&isp1_mmu>;
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status = "disabled";
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};
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rga: rga@ff680000 {
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compatible = "rockchip,rga2";
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dev_mode = <1>;
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reg = <0x0 0xff680000 0x0 0x1000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
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clock-names = "aclk_rga", "hclk_rga", "clk_rga";
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power-domains = <&power RK3399_PD_RGA>;
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status = "okay";
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};
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};
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&display_subsystem {
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status = "disabled";
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ports = <&vopb_out>, <&vopl_out>;
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logo-memory-region = <&drm_logo>;
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route {
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route_hdmi: route-hdmi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_hdmi>;
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};
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route_dsi: route-dsi {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_dsi>;
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};
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route_edp: route-edp {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_edp>;
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};
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};
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};
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&edp {
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/delete-property/pinctrl-names;
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/delete-property/pinctrl-0;
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};
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&iep {
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status = "okay";
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};
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&iep_mmu {
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status = "okay";
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};
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&mpp_srv {
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status = "okay";
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};
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&pvtm {
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status = "okay";
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};
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&rkvdec {
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status = "okay";
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/* 0 means ion, 1 means drm */
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//allocator = <0>;
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};
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&rkvdec_mmu {
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status = "okay";
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};
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&vdpu {
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status = "okay";
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};
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&vepu {
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status = "okay";
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};
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&vpu_mmu {
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status = "okay";
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};
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&uart2 {
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status = "disabled";
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};
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&pinctrl {
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isp {
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cif_clkout: cif-clkout {
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rockchip,pins =
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/* cif_clkout */
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<2 RK_PB3 3 &pcfg_pull_none>;
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};
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isp_dvp_d0d7: isp-dvp-d0d7 {
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rockchip,pins =
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<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
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/* cif_clkout */
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<2 RK_PB3 3 &pcfg_pull_none>,
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/* cif_data0 */
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<2 RK_PA0 3 &pcfg_pull_none>,
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/* cif_data1 */
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<2 RK_PA1 3 &pcfg_pull_none>,
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/* cif_data2 */
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<2 RK_PA2 3 &pcfg_pull_none>,
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/* cif_data3 */
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<2 RK_PA3 3 &pcfg_pull_none>,
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/* cif_data4 */
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<2 RK_PA4 3 &pcfg_pull_none>,
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/* cif_data5 */
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<2 RK_PA5 3 &pcfg_pull_none>,
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/* cif_data6 */
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<2 RK_PA6 3 &pcfg_pull_none>,
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/* cif_data7 */
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<2 RK_PA7 3 &pcfg_pull_none>,
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/* cif_sync */
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<2 RK_PB0 3 &pcfg_pull_none>,
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/* cif_href */
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<2 RK_PB1 3 &pcfg_pull_none>,
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/* cif_clkin */
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<2 RK_PB2 3 &pcfg_pull_none>;
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};
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isp_shutter: isp-shutter {
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rockchip,pins =
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/* SHUTTEREN */
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<1 RK_PA1 1 &pcfg_pull_none>,
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/* SHUTTERTRIG */
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<1 RK_PA0 1 &pcfg_pull_none>;
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};
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isp_flash_trigger: isp-flash-trigger {
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/* ISP_FLASHTRIGOU */
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rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>;
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};
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isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
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/* ISP_FLASHTRIGOU */
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rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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cam_pins {
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cam0_default_pins: cam0-default-pins {
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rockchip,pins =
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<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>,
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<2 RK_PB3 3 &pcfg_pull_none>;
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};
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cam0_sleep_pins: cam0-sleep-pins {
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rockchip,pins =
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<4 RK_PD3 3 &pcfg_pull_none>,
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<2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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