145 lines
2.3 KiB
Plaintext
145 lines
2.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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/dts-v1/;
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#include "rk3288-evb-rk628.dtsi"
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/ {
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model = "Rockchip RK3288 EVB RK628 Board";
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compatible = "rockchip,rk3288-evb-rk628", "rockchip,rk3288";
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panel {
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compatible = "simple-panel";
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backlight = <&backlight>;
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enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
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prepare-delay-ms = <20>;
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enable-delay-ms = <20>;
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disable-delay-ms = <20>;
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unprepare-delay-ms = <20>;
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bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <48000000>;
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hactive = <1024>;
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vactive = <600>;
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hback-porch = <90>;
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hfront-porch = <90>;
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vback-porch = <10>;
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vfront-porch = <10>;
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hsync-len = <90>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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port {
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panel_in_lvds: endpoint {
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remote-endpoint = <&lvds_out_panel>;
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};
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};
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};
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};
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&rk628_lvds {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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lvds_in_post_process: endpoint {
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remote-endpoint = <&post_process_out_lvds>;
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};
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};
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port@1 {
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reg = <1>;
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lvds_out_panel: endpoint {
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remote-endpoint = <&panel_in_lvds>;
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};
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};
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};
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};
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&rk628_combtxphy {
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status = "okay";
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};
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&rk628_post_process {
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pinctrl-names = "default";
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pinctrl-0 = <&rk628_vop_pins>;
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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post_process_in_rgb: endpoint {
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remote-endpoint = <&rgb_out_post_process>;
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};
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};
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port@1 {
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reg = <1>;
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post_process_out_lvds: endpoint {
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remote-endpoint = <&lvds_in_post_process>;
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};
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};
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};
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};
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&rgb {
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status = "okay";
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ports {
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port@1 {
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reg = <1>;
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rgb_out_post_process: endpoint {
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remote-endpoint = <&post_process_in_rgb>;
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};
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};
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};
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};
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&video_phy {
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status = "okay";
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};
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&rgb_in_vopb {
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status = "disabled";
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};
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&rgb_in_vopl {
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status = "okay";
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};
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&route_rgb {
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connect = <&vopl_out_rgb>;
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status = "disabled";
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};
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&vopb {
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assigned-clocks = <&cru DCLK_VOP0>;
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assigned-clock-parents = <&cru PLL_GPLL>;
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};
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&vopl {
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assigned-clocks = <&cru DCLK_VOP1>;
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assigned-clock-parents = <&cru PLL_CPLL>;
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};
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