70 lines
2.6 KiB
Diff
70 lines
2.6 KiB
Diff
From 5e2ba0042bf530c7c50468eeac24f6c2b71d494a Mon Sep 17 00:00:00 2001
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From: Jeffy Chen <jeffy.chen@rock-chips.com>
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Date: Mon, 30 May 2022 15:25:32 +0800
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Subject: [PATCH] arm64 front end: add support for 'ldnp', 'stnp'
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Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
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---
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VEX/priv/guest_arm64_toIR.c | 14 +++++++++++---
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1 file changed, 11 insertions(+), 3 deletions(-)
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diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
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index 44a1c23..d406fcf 100644
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--- a/VEX/priv/guest_arm64_toIR.c
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+++ b/VEX/priv/guest_arm64_toIR.c
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@@ -5006,13 +5006,16 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
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}
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}
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- /* -------- LDP,STP (immediate, simm7) (INT REGS) -------- */
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+ /* -------- LDP,STP,LDNP,STNP (immediate, simm7) (INT REGS) -------- */
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/* L==1 => mm==LD
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L==0 => mm==ST
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x==0 => 32 bit transfers, and zero extended loads
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x==1 => 64 bit transfers
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simm7 is scaled by the (single-register) transfer size
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+ (at-Rn-then-Rn=EA (non-temporal))
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+ x0 101 0000 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP], #imm
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+
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(at-Rn-then-Rn=EA)
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x0 101 0001 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP], #imm
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@@ -5023,12 +5026,13 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
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x0 101 0010 L imm7 Rt2 Rn Rt1 mmP Rt1,Rt2, [Xn|SP, #imm]
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*/
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UInt insn_30_23 = INSN(30,23);
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- if (insn_30_23 == BITS8(0,1,0,1,0,0,0,1)
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+ if (insn_30_23 == BITS8(0,1,0,1,0,0,0,0)
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+ || insn_30_23 == BITS8(0,1,0,1,0,0,0,1)
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|| insn_30_23 == BITS8(0,1,0,1,0,0,1,1)
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|| insn_30_23 == BITS8(0,1,0,1,0,0,1,0)) {
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UInt bL = INSN(22,22);
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UInt bX = INSN(31,31);
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- UInt bWBack = INSN(23,23);
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+ UInt bWBack = INSN(24,23) != BITS2(1,0);
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UInt rT1 = INSN(4,0);
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UInt rN = INSN(9,5);
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UInt rT2 = INSN(14,10);
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@@ -5049,6 +5053,7 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
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IRTemp tTA = newTemp(Ity_I64);
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IRTemp tWA = newTemp(Ity_I64);
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switch (INSN(24,23)) {
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+ case BITS2(0,0): /* fallthru */
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case BITS2(0,1):
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assign(tTA, mkexpr(tRN)); assign(tWA, mkexpr(tEA)); break;
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case BITS2(1,1):
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@@ -5109,6 +5114,9 @@ Bool dis_ARM64_load_store(/*MB_OUT*/DisResult* dres, UInt insn,
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const HChar* fmt_str = NULL;
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switch (INSN(24,23)) {
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+ case BITS2(0,0):
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+ fmt_str = "%snp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA (non-temporal))\n";
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+ break;
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case BITS2(0,1):
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fmt_str = "%sp %s, %s, [%s], #%lld (at-Rn-then-Rn=EA)\n";
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break;
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--
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2.20.1
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