/*
 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

/ {
	aliases {
		mmc0 = &sdhci;
		mmc1 = &sdmmc;
	};

	chosen {
		stdout-path = &uart2;
		u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
	};

	secure-otp@ffcd0000 {
		compatible = "rockchip,rk3528-secure-otp";
		reg = <0x0 0xffcd0000 0x0 0x4000>;
		secure_conf = <0xff4500c0>;
		mask_addr = <0x0>;
		cru_rst_addr = <0xff4a8080>;
		u-boot,dm-spl;
		status = "okay";
	};

};

&grf {
	u-boot,dm-spl;
	status = "okay";
};

&ioc_grf {
	u-boot,dm-spl;
	status = "okay";
};

&cru {
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	u-boot,dm-spl;
	status = "okay";
};

&crypto {
	u-boot,dm-spl;
	status = "okay";
};

&rng {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&psci {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&uart2 {
	clock-frequency = <24000000>;
	u-boot,dm-spl;
	status = "okay";
};

&sfc {
	u-boot,dm-spl;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	status = "okay";

	#address-cells = <1>;
	#size-cells = <0>;
	spi_nand: flash@0 {
		u-boot,dm-spl;
		compatible = "spi-nand";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <75000000>;
	};

	spi_nor: flash@1 {
		u-boot,dm-spl;
		compatible = "jedec,spi-nor";
		label = "sfc_nor";
		reg = <0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <100000000>;
	};
};

&sdhci {
	bus-width = <8>;
	u-boot,dm-spl;
	/delete-property/ assigned-clocks;
	/delete-property/ assigned-clock-rates;
	/delete-property/ pinctrl-names;
	/delete-property/ pinctrl-0;
	mmc-hs400-1_8v;
	mmc-hs400-enhanced-strobe;
	fixed-emmc-driver-type = <1>;
	status = "okay";
};

&sdmmc {
	u-boot,dm-spl;
	status = "okay";
};

&saradc {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&u2phy_otg {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&usb2phy {
	u-boot,dm-pre-reloc;
	status = "okay";
};

&firmware {
	u-boot,dm-spl;
};

&scmi {
	u-boot,dm-spl;
};

&scmi_clk {
	u-boot,dm-spl;
};

&scmi_shmem {
	u-boot,dm-spl;
};

&pinctrl {
	u-boot,dm-spl;
	status = "okay";
};

&gpio0 {
	u-boot,dm-spl;
};

&gpio1 {
	u-boot,dm-spl;
};

&gpio2 {
	u-boot,dm-spl;
};

&pcfg_pull_none_drv_level_1 {
	u-boot,dm-spl;
};

&pcfg_pull_none_drv_level_2 {
	u-boot,dm-spl;
};

&pcfg_pull_up_drv_level_1 {
	u-boot,dm-spl;
};

&pcfg_pull_up_drv_level_2 {
	u-boot,dm-spl;
};

&pcfg_pull_up {
	u-boot,dm-spl;
};

&pcfg_pull_none {
	u-boot,dm-spl;
};

&sdmmc_pins {
	u-boot,dm-spl;
};

&sdmmc_bus4 {
	u-boot,dm-spl;
};

&sdmmc_clk {
	u-boot,dm-spl;
};

&sdmmc_cmd {
	u-boot,dm-spl;
};

&sdmmc_det {
	u-boot,dm-spl;
};