392 lines
9.4 KiB
Plaintext
392 lines
9.4 KiB
Plaintext
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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#include <dt-bindings/reset/rk628-rgu.h>
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#include <dt-bindings/clock/rk628-cgu.h>
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/ {
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rk628_xin_osc0_func: rk628-xin-osc0-func {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "rk628_xin_osc0_func";
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};
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rk628_xin_osc0_half: rk628-xin-osc0-half {
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compatible = "fixed-factor-clock";
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#clock-cells = <0>;
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clocks = <&rk628_xin_osc0_func>;
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clock-mult = <1>;
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clock-div = <2>;
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clock-output-names = "rk628_xin_osc0_half";
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};
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};
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&rk628 {
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compatible = "rockchip,rk628";
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rk628_cru: cru {
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compatible = "rockchip,rk628-cru";
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#clock-cells = <1>;
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#reset-cells = <1>;
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status = "okay";
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};
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rk628_efuse: efuse {
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compatible = "rockchip,rk628-efuse";
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clocks = <&rk628_cru CGU_PCLK_EFUSE>;
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clock-names = "pclk";
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resets = <&rk628_cru RGU_EFUSE>;
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#phy-cells = <0>;
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status = "disabled";
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};
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rk628_pinctrl: pinctrl {
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compatible = "rockchip,rk628-pinctrl";
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status = "okay";
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rk628_gpio0: rk628-gpio0 {
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clocks = <&rk628_cru CGU_PCLK_GPIO0>;
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clock-names = "pclk";
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resets = <&rk628_cru RGU_GPIO0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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rk628_gpio1: rk628-gpio1 {
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clocks = <&rk628_cru CGU_PCLK_GPIO1>;
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clock-names = "pclk";
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resets = <&rk628_cru RGU_GPIO1>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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rk628_gpio2: rk628-gpio2 {
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clocks = <&rk628_cru CGU_PCLK_GPIO2>;
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clock-names = "pclk";
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resets = <&rk628_cru RGU_GPIO2>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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rk628_gpio3: rk628-gpio3 {
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clocks = <&rk628_cru CGU_PCLK_GPIO3>;
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clock-names = "pclk";
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resets = <&rk628_cru RGU_GPIO3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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rk628_i2sm0_pins: i2sm0 {
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pins = "gpio0a2", /* i2sm0_sck */
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"gpio0a3", /* i2sm0_lr */
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"gpio0a4", /* i2sm0_d0 */
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"gpio0a5", /* i2sm0_d1 */
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"gpio0a6", /* i2sm0_d2 */
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"gpio0a7"; /* i2sm0_d3 */
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function = "i2sm0";
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};
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rk628_hpd_in_pins: hpd-in {
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pins = "gpio0b0";
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function = "hpd_in";
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};
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rk628_ddc_tx_pins: ddc-tx {
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pins = "gpio0b1", /* ddc_tx_sda */
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"gpio0b2"; /* ddc_tx_scl */
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function = "ddc_tx";
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};
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rk628_cec_tx_pins: cec-tx {
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pins = "gpio0b3";
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function = "cec_tx";
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};
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rk628_test_clkout_pins: test-clkout {
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pins = "gpio1a0";
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function = "test_clkout";
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};
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rk628_i2sm1_pins: i2sm1 {
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pins = "gpio1a2", /* i2sm1_sck */
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"gpio1a3", /* i2sm1_lr */
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"gpio1a4", /* i2sm1_d0 */
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"gpio1a5", /* i2sm1_d1 */
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"gpio1a6", /* i2sm1_d2 */
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"gpio1a7"; /* i2sm1_d3 */
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function = "i2sm1";
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};
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rk628_hpdm0_out_pins: hpdm0-out {
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pins = "gpio1b0";
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function = "hpdm0_out";
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};
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rk628_ddcm0_rx_pins: ddcm0-rx {
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pins = "gpio1b1", /* ddcm0_rx_sda */
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"gpio1b2"; /* ddcm0_rx_scl */
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function = "ddcm0_rx";
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};
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rk628_cecm0_rx_pins: cecm0_rx {
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pins = "gpio1b3";
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function = "cecm0_rx";
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};
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rk628_vop_pins: vop {
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pins = "gpio2a0", /* vop_d0 */
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"gpio2a1", /* vop_d1 */
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"gpio2a2", /* vop_d2 */
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"gpio2a3", /* vop_d3 */
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"gpio2a4", /* vop_d4 */
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"gpio2a5", /* vop_d5 */
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"gpio2a6", /* vop_d6 */
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"gpio2a7", /* vop_d7 */
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"gpio2b0", /* vop_d8 */
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"gpio2b1", /* vop_d9 */
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"gpio2b2", /* vop_d10 */
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"gpio2b3", /* vop_d11 */
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"gpio2b4", /* vop_d12 */
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"gpio2b5", /* vop_d13 */
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"gpio2b6", /* vop_d14 */
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"gpio2b7", /* vop_d15 */
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"gpio2c0", /* vop_d16 */
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"gpio2c1", /* vop_d17 */
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"gpio2c2", /* vop_d18 */
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"gpio2c3", /* vop_d19 */
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"gpio2c4", /* vop_d20 */
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"gpio2c5", /* vop_d21 */
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"gpio2c6", /* vop_d22 */
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"gpio2c7", /* vop_d23 */
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"gpio3a0", /* vop_den */
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"gpio3a1", /* vop_hsync */
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"gpio3a3", /* vop_vsync */
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"gpio3b0"; /* vop_dclk */
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function = "vop";
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drive-strength = <1>;
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};
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rk628_hpdm1_out: hpdm1-out {
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pins = "gpio3a4";
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function = "hpdm1_out";
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};
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rk628_ddcm1_rx_pins: ddcm1-rx {
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pins = "gpio3a5", /* ddcm1_rx_sda */
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"gpio3a6"; /* ddcm1_rx_scl */
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function = "ddcm1_rx";
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};
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rk628_cecm1_rx_pins: cecm1-rx {
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pins = "gpio3a7";
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function = "cecm1_rx";
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};
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rk628_gvi_hpd_pins: gvi-hpd {
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pins = "gpio3b1";
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function = "gvi_hpd";
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};
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rk628_gvi_lock_pins: gvi-lock {
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pins = "gpio3b2";
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function = "gvi_lock";
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};
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rk628_hdmirx_cec0: hdmirx-cec0 {
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pins = "hdmirx_cec";
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function = "hdmirx_cec0";
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};
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rk628_hdmirx_cec1: hdmirx-cec1 {
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pins = "hdmirx_cec";
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function = "hdmirx_cec1";
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};
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rk628_rxddc_input0: rxddc-input0 {
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pins = "rxddc_scl",
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"rxddc_sda";
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function = "rxddc_input0";
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};
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rk628_rxddc_input1: rxddc-input1 {
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pins = "rxddc_scl",
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"rxddc_sda";
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function = "rxddc_input1";
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};
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rk628_i2sm0_input: i2sm0-input {
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pins = "i2sm_sck",
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"i2sm_d",
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"i2sm_lr";
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function = "i2sm0_input";
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};
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rk628_i2sm1_input: i2sm1-input {
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pins = "i2sm_sck",
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"i2sm_d",
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"i2sm_lr";
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function = "i2sm1_input";
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};
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};
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rk628_combtxphy: combtxphy {
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compatible = "rockchip,rk628-combtxphy";
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clocks = <&rk628_cru CGU_PCLK_TXPHY_CON>, <&rk628_cru CGU_SCLK_VOP>;
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clock-names = "pclk", "ref_clk";
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resets = <&rk628_cru RGU_TXPHY_CON>;
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#phy-cells = <0>;
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status = "disabled";
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};
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rk628_combrxphy: combrxphy {
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compatible = "rockchip,rk628-combrxphy";
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clocks = <&rk628_cru CGU_PCLK_RXPHY>;
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clock-names = "pclk";
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resets = <&rk628_cru RGU_RXPHY>;
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#phy-cells = <0>;
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status = "disabled";
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};
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rk628_dsi0: dsi0 {
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compatible = "rockchip,rk628-dsi0";
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clocks = <&rk628_cru CGU_PCLK_DSI0>,
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<&rk628_cru CGU_CLK_CFG_DPHY0>;
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clock-names = "pclk", "cfg";
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resets = <&rk628_cru RGU_DSI0>;
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phys = <&rk628_combtxphy>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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rk628_dsi1: dsi1 {
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compatible = "rockchip,rk628-dsi1";
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clocks = <&rk628_cru CGU_PCLK_DSI1>,
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<&rk628_cru CGU_CLK_CFG_DPHY1>;
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clock-names = "pclk", "cfg";
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resets = <&rk628_cru RGU_DSI1>;
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phys = <&rk628_combtxphy>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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rk628_lvds: lvds {
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compatible = "rockchip,rk628-lvds";
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phys = <&rk628_combtxphy>;
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status = "disabled";
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};
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rk628_gvi: gvi {
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compatible = "rockchip,rk628-gvi";
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clocks = <&rk628_cru CGU_PCLK_GVIHOST>;
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clock-names = "pclk";
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resets = <&rk628_cru RGU_GVIHOST>;
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phys = <&rk628_combtxphy>;
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status = "disabled";
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};
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rk628_rgb_tx: rgb-tx {
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compatible = "rockchip,rk628-rgb-tx";
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status = "disabled";
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};
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rk628_yuv_rx: yuv-rx {
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compatible = "rockchip,rk628-yuv-rx";
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status = "disabled";
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};
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rk628_yuv_tx: yuv-tx {
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compatible = "rockchip,rk628-yuv-tx";
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status = "disabled";
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};
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rk628_bt1120_rx: bt1120-rx {
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compatible = "rockchip,rk628-bt1120-rx";
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clocks = <&rk628_cru CGU_BT1120DEC>;
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clock-names = "bt1120dec";
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resets = <&rk628_cru RGU_BT1120DEC>;
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status = "disabled";
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};
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rk628_bt1120_tx: bt1120-tx {
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compatible = "rockchip,rk628-bt1120-tx";
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status = "disabled";
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};
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rk628_post_process: post-process {
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compatible = "rockchip,rk628-post-process";
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clocks = <&rk628_cru CGU_SCLK_VOP>,
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<&rk628_cru CGU_CLK_RX_READ>;
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clock-names = "sclk_vop", "rx_read";
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resets = <&rk628_cru RGU_DECODER>,
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<&rk628_cru RGU_CLK_RX>,
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<&rk628_cru RGU_VOP>;
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reset-names = "decoder", "clk_rx", "vop";
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status = "disabled";
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};
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rk628_hdmi: hdmi {
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compatible = "rockchip,rk628-hdmi";
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clocks = <&rk628_cru CGU_PCLK_HDMITX>,
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<&rk628_cru CGU_SCLK_VOP>;
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clock-names = "pclk", "dclk";
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pinctrl-names = "default";
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pinctrl-0 = <&rk628_hpd_in_pins &rk628_ddc_tx_pins &rk628_i2sm0_pins>;
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#sound-dai-cells = <0>;
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status = "disabled";
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};
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rk628_hdmirx: hdmirx {
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compatible = "rockchip,rk628-hdmirx";
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clocks = <&rk628_cru CGU_PCLK_HDMIRX>,
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<&rk628_cru CGU_CLK_HDMIRX_CEC>,
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<&rk628_cru CGU_CLK_HDMIRX_AUD>,
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<&rk628_cru CGU_CLK_IMODET>;
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clock-names = "pclk", "cec", "audio", "imodet";
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resets = <&rk628_cru RGU_HDMIRX>,
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<&rk628_cru RGU_HDMIRX_PON>;
|
||
|
|
reset-names = "hdmirx", "hdmirx_pon";
|
||
|
|
phys = <&rk628_combrxphy>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
rk628_csi: csi {
|
||
|
|
compatible = "rockchip,rk628-csi";
|
||
|
|
clocks = <&rk628_cru CGU_PCLK_HDMIRX>,
|
||
|
|
<&rk628_cru CGU_CLK_IMODET>,
|
||
|
|
<&rk628_cru CGU_CLK_HDMIRX_AUD>,
|
||
|
|
<&rk628_cru CGU_CLK_HDMIRX_CEC>,
|
||
|
|
<&rk628_cru CGU_SCLK_VOP>,
|
||
|
|
<&rk628_cru CGU_CLK_RX_READ>,
|
||
|
|
<&rk628_cru CGU_PCLK_CSI>,
|
||
|
|
<&rk628_cru CGU_CLK_TESTOUT>;
|
||
|
|
clock-names = "hdmirx", "imodet", "hdmirx_aud", "hdmirx_cec",
|
||
|
|
"vop", "rx_read", "csi0", "i2s_mclk";
|
||
|
|
assigned-clocks = <&rk628_cru CGU_CLK_TESTOUT>;
|
||
|
|
assigned-clock-parents = <&rk628_cru CGU_CLK_HDMIRX_AUD>;
|
||
|
|
resets = <&rk628_cru RGU_HDMIRX>,
|
||
|
|
<&rk628_cru RGU_HDMIRX_PON>,
|
||
|
|
<&rk628_cru RGU_DECODER>,
|
||
|
|
<&rk628_cru RGU_CLK_RX>,
|
||
|
|
<&rk628_cru RGU_VOP>,
|
||
|
|
<&rk628_cru RGU_CSI>;
|
||
|
|
reset-names = "hdmirx", "hdmirx_pon", "decoder", "clk_rx",
|
||
|
|
"vop", "csi0";
|
||
|
|
phys = <&rk628_combrxphy>, <&rk628_combtxphy>;
|
||
|
|
phy-names = "combrxphy", "combtxphy";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&rk628_hpdm0_out_pins &rk628_ddcm0_rx_pins &rk628_i2sm0_pins &rk628_test_clkout_pins>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
};
|